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*
Some fixes in libs/minisat (thanks to Siesh1oo)
Clifford Wolf
2014-03-12
*
- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar...
Siesh1oo
2014-03-12
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Fixed dependencies of "make test"
Clifford Wolf
2014-03-12
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Added libs/minisat (copy of minisat git master)
Clifford Wolf
2014-03-12
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OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/...
Clifford Wolf
2014-03-11
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Merged addition of SED makefile variable from github.com/Siesh1oo/yosys
Clifford Wolf
2014-03-11
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Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
Clifford Wolf
2014-03-11
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Added support for `line compiler directive
Clifford Wolf
2014-03-11
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Fixed memory corruption in passes/abc/blifparse.cc
Clifford Wolf
2014-03-11
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Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh
Clifford Wolf
2014-03-11
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Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)
Clifford Wolf
2014-03-11
*
Fixed a typo in RTLIL::Module::addReduce...
Clifford Wolf
2014-03-10
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Improved verific command (added support for some operators)
Clifford Wolf
2014-03-10
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Improvements in verific command
Clifford Wolf
2014-03-10
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Added RTLIL::Module::add... helper methods
Clifford Wolf
2014-03-10
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Added "verific" command
Clifford Wolf
2014-03-09
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Fixed dumping of timing() { .. } block in libparse
Clifford Wolf
2014-03-09
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Verbose reading of liberty and constr files in ABC pass
Clifford Wolf
2014-03-09
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Fixed bug in freduce command
Clifford Wolf
2014-03-07
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Some minor code cleanups in freduce command
Clifford Wolf
2014-03-07
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Bugfix in ilang frontend autoidx recovery
Clifford Wolf
2014-03-07
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Use log_abort() and log_assert() in BTOR backend
Clifford Wolf
2014-03-07
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Added freduce -dump
Clifford Wolf
2014-03-06
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Added freduce -stop
Clifford Wolf
2014-03-06
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Fixed gcc compiler warning
Clifford Wolf
2014-03-06
*
Fixed undef handling in opt_reduce
Clifford Wolf
2014-03-06
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Fixes for improved techmap of shifts with large B inputs
Clifford Wolf
2014-03-06
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Fixed use of frozen literals in SatGen
Clifford Wolf
2014-03-06
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Strictly zero-extend unsigned A-inputs of shift operations in techmap
Clifford Wolf
2014-03-06
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Added techmap -max_iter option
Clifford Wolf
2014-03-06
*
Improved techmap of shift with wide B inputs
Clifford Wolf
2014-03-06
*
Strictly zero-extend unsigned A-inputs of shift operations
Clifford Wolf
2014-03-06
*
Switched to EZMINISAT_SIMPSOLVER as default SAT solver
Clifford Wolf
2014-03-05
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Include id2ast pointers when dumping AST
Clifford Wolf
2014-03-05
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Fixed merging of compatible wire decls in AST frontend
Clifford Wolf
2014-03-05
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Bugfix in recursive AST simplification
Clifford Wolf
2014-03-05
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fixed freduce for Minisat::SimpSolver: use frozen_literal()
Clifford Wolf
2014-03-03
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ezSAT: Added frozen_literal() API
Clifford Wolf
2014-03-03
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ezSAT: Fixed handling of eliminated Literals, added auto-freeze for expressions
Clifford Wolf
2014-03-03
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Added ezSAT::eliminated API to help the SAT solver remember eliminated variables
Clifford Wolf
2014-03-01
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ezSAT bugfix: don't call virtual methods in base class constructor
Clifford Wolf
2014-03-01
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Removed ezSAT::assumed() API
Clifford Wolf
2014-03-01
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Removed ezSAT built-in brute-froce solver
Clifford Wolf
2014-03-01
*
Fixed vhdl2verilog temp dir name
Clifford Wolf
2014-03-01
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Fixed vhdl2verilog help message
Clifford Wolf
2014-03-01
*
Fixed const folding of $bu0 cells
Clifford Wolf
2014-02-27
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Fixed bit-extending in $mux argument (use $bu0 instead of $pos)
Clifford Wolf
2014-02-26
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Added support for $bu0 to SatGen
Clifford Wolf
2014-02-26
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Don't blow up constants unneccessarily in Verilog frontend
Clifford Wolf
2014-02-24
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Added support for Minisat::SimpSolver + ezSAT frezze() API
Clifford Wolf
2014-02-23
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