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Merge branch 'bugfix'
Clifford Wolf
2013-05-16
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Fixed synthesis of functions in latched blocks
Clifford Wolf
2013-05-16
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Some improvements in vcdcd.pl
Clifford Wolf
2013-05-14
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Added support for verilog === operator
Clifford Wolf
2013-05-07
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Added tcl "yosys -import" command
Clifford Wolf
2013-05-02
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Improved/simplified TCL bindings
Clifford Wolf
2013-05-01
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Added support for const cell inputs in techmap
Clifford Wolf
2013-04-27
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Fixed README for new show command behavior (svg vs. ps)
Clifford Wolf
2013-04-27
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Added "flatten" pass
Clifford Wolf
2013-04-26
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Fixed handling of positional module parameters
Clifford Wolf
2013-04-26
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Fixed hierarchy pass for hierarchies of parametric modules
Clifford Wolf
2013-04-26
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Only use sha1 checksums for names of parametric modules when the verbose form...
Clifford Wolf
2013-04-26
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Fixed "show -format ..." command line parsing
Clifford Wolf
2013-04-15
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Added "submod -name ..." support
Clifford Wolf
2013-04-15
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Fixed a bug in AST frontend for cases with non-blocking assigned variables as...
Clifford Wolf
2013-04-13
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Fixed a bug in opt_const when optimizing 1-bit compares with constants
Clifford Wolf
2013-04-13
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Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2013-04-07
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Merge pull request #5 from hansiglaser/master
Clifford Wolf
2013-04-05
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fsm_export: optionally use binary state encoding as state names instead of
Johann Glaser
2013-04-05
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Merge pull request #4 from hansiglaser/master
Clifford Wolf
2013-04-05
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fsm_export: specify KISS filename on command line
Johann Glaser
2013-04-05
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Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v
Clifford Wolf
2013-04-07
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Fixed/improved handling of colored wires in show command
Clifford Wolf
2013-04-01
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Added support for @<set-name> in expand select ops (%x, %ci, %co)
Clifford Wolf
2013-04-01
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Removed 4096 bytes limit for size of command from script file
Clifford Wolf
2013-04-01
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Added -color <color> <selection> option to show command
Clifford Wolf
2013-04-01
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Fixed "select" for "%%" stmt with emty stack
Clifford Wolf
2013-03-31
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Added "script" command
Clifford Wolf
2013-03-31
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Now only use value from "initial" when no matching "always" block is found
Clifford Wolf
2013-03-31
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Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
Clifford Wolf
2013-03-31
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
Clifford Wolf
2013-03-31
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Added k68 (m68k compatible cpu) test case from verilator
Clifford Wolf
2013-03-31
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Improved opt_share for reduce cells
Clifford Wolf
2013-03-29
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Improved opt_share for commutative standard cells
Clifford Wolf
2013-03-29
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Added EXTRA_TARGETS Makefile variable
Clifford Wolf
2013-03-28
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Improved Makefile: Added ENABLE_* switches
Clifford Wolf
2013-03-28
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Implemented TCL support (only via -c option at the moment)
Clifford Wolf
2013-03-28
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Improved subcircuit verbose output (added portmapper results)
Clifford Wolf
2013-03-28
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Fixed svgviewer hacks for builtin files
Clifford Wolf
2013-03-28
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Added proper TECHMAP_FAIL support and added support for the celltype attribut...
Clifford Wolf
2013-03-28
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Implemented proper handling of stub placeholder modules
Clifford Wolf
2013-03-28
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Keep viewport transform stable on reload in yosys-svgviewer
Clifford Wolf
2013-03-27
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Added check: only one module for "show" unless format is "ps"
Clifford Wolf
2013-03-27
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Now using SVG and yosys-svgviewer per default in show command
Clifford Wolf
2013-03-27
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Added yosys-svgviewer to build system and renamed filterlib to yosys-filterlib
Clifford Wolf
2013-03-27
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Imported svgviewer from qt4.8
Clifford Wolf
2013-03-27
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Create nice errors when calling RTLIL::Module::derive() of base class
Clifford Wolf
2013-03-26
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Collect parameters in hierarchy -generate (and do nothing with them)
Clifford Wolf
2013-03-26
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Tiny bugfix in simlib.v
Clifford Wolf
2013-03-26
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Improvements and bugfixes for generate blocks with local signals
Clifford Wolf
2013-03-26
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