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Debian dgit repo for package yosys
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Replaced "#ifdef WIN32" with "#ifdef _WIN32"
Clifford Wolf
2014-10-09
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Added API for generic cell cost calculations
Clifford Wolf
2014-10-09
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added .exe and .html output files to .gitignore
Clifford Wolf
2014-10-09
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No rusage on win32
Clifford Wolf
2014-10-09
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Added mxe-based cross build for win32
Clifford Wolf
2014-10-09
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Fixes in "hilomap" help message
Clifford Wolf
2014-10-08
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sort cell types in "stat" output by name
Clifford Wolf
2014-10-03
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sat encoding for exclusive $pmux ctrl inputs in "share" pass
Clifford Wolf
2014-10-03
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satgen import sigbit api
Clifford Wolf
2014-10-03
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added resource sharing of $macc cells
Clifford Wolf
2014-10-03
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Added $_BUF_ cell type
Clifford Wolf
2014-10-03
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remove buffers in opt_clean
Clifford Wolf
2014-10-03
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resource sharing of $alu cells
Clifford Wolf
2014-10-03
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set "keep" on modules with $assert cells in "hierarchy"
Clifford Wolf
2014-09-30
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Added support for "keep" on modules
Clifford Wolf
2014-09-29
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namespace Yosys
Clifford Wolf
2014-09-27
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Merge pull request #39 from ahmedirfan1983/master
Clifford Wolf
2014-09-22
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merged with current mas.ter branch + features added + bug fixes
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Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
Ahmed Irfan
2014-09-22
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added case for memwr cell that is used in muxes (same cell is used more than one time) corrected bug for xnor and logic_not added pmux cell translation Conflicts: backends/btor/btor.cc
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Re-enabled assert for new logic loops in "share" pass
Clifford Wolf
2014-09-21
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Various improvements regarding logic loops in "share" results
Clifford Wolf
2014-09-21
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Logic loop bugfix for "share" pass
Clifford Wolf
2014-09-21
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Added "share -limit"
Clifford Wolf
2014-09-21
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Still loop bug in "share": changed assert to warning
Clifford Wolf
2014-09-21
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Do not introduce new logic loops in "share"
Clifford Wolf
2014-09-21
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Assert on new logic loops in "share" pass
Clifford Wolf
2014-09-21
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Added "test_abcloop" command
Clifford Wolf
2014-09-19
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Initialize RTLIL::Const from std::vector<bool>
Clifford Wolf
2014-09-19
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Sorting of object names in ilang backend
Clifford Wolf
2014-09-19
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Small improvements in "abc" command handle_loops() function
Clifford Wolf
2014-09-19
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Using "NOT" instead of "INV" as cell name in default abc genlib file
Clifford Wolf
2014-09-19
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Alphabetically sort port names in "show" output
Clifford Wolf
2014-09-19
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Do not run "scorr" in "abc -fast"
Clifford Wolf
2014-09-18
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Improvements in "synth" script
Clifford Wolf
2014-09-18
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Added "abc -fast"
Clifford Wolf
2014-09-18
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Added commit count to devel version number
Clifford Wolf
2014-09-17
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Fixed $_NOR vs. $_NOR_ typo in abc.cc
Clifford Wolf
2014-09-16
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Fixed $memwr/$memrd order in memory_dff
Clifford Wolf
2014-09-16
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Added new CodingReadme file (replaces CodingStyle and CHECKLISTS)
Clifford Wolf
2014-09-16
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Fixed $macc simlib model for zero-config
Clifford Wolf
2014-09-16
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More aggressive $macc merging in alumacc
Clifford Wolf
2014-09-15
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Added the obvious optimizations to alumacc $macc generator
Clifford Wolf
2014-09-15
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Improved maccmap tree bit packing
Clifford Wolf
2014-09-15
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Fixed wreduce $shiftx handling
Clifford Wolf
2014-09-15
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Fixed monitor notifications for removed cell
Clifford Wolf
2014-09-14
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Added "synth" command
Clifford Wolf
2014-09-14
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Fixed techmap_wrap for techmap_celltype
Clifford Wolf
2014-09-14
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Using alumacc in techmap.v
Clifford Wolf
2014-09-14
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Various fixes/cleanups in alumacc and maccmap
Clifford Wolf
2014-09-14
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Added techmap_wrap attribute
Clifford Wolf
2014-09-14
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alumacc fix for $pos cells
Clifford Wolf
2014-09-14
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