yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Only initialize TCL interpreter when needed	Clifford Wolf	2013-05-23
*	Fixed memory leak in ilang frontend	Clifford Wolf	2013-05-23
*	Added missing newline to some error messages	Clifford Wolf	2013-05-23
*	Added labels to "help -write-tex-command-reference-manual" output	Clifford Wolf	2013-05-23
*	Added support for processes to show command	Clifford Wolf	2013-05-23
*	Fixed show command for constant assignments	Clifford Wolf	2013-05-23
*	Some improvements in opt_rmdff	Clifford Wolf	2013-05-23
*	Merge pull request #6 from hansiglaser/master	Clifford Wolf	2013-05-19
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\| *	added option '-Dname[=definition]' to command 'read_verilog'	Johann Glaser	2013-05-19
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*	Removed test cases that have been moved to yosys-test.	Clifford Wolf	2013-05-17
*	Fixed to aggressive x-folding in opt_const	Clifford Wolf	2013-05-17
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-05-16
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\| *	Improved vcdcd.pl (added -d option)	Clifford Wolf	2013-05-14
* \|	Merge branch 'bugfix'	Clifford Wolf	2013-05-16
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\| *	Fixed synthesis of functions in latched blocks	Clifford Wolf	2013-05-16
* \|	Some improvements in vcdcd.pl	Clifford Wolf	2013-05-14
* \|	Added support for verilog === operator	Clifford Wolf	2013-05-07
* \|	Added tcl "yosys -import" command	Clifford Wolf	2013-05-02
* \|	Improved/simplified TCL bindings	Clifford Wolf	2013-05-01
* \|	Added support for const cell inputs in techmap	Clifford Wolf	2013-04-27
* \|	Fixed README for new show command behavior (svg vs. ps)	Clifford Wolf	2013-04-27
* \|	Added "flatten" pass	Clifford Wolf	2013-04-26
* \|	Fixed handling of positional module parameters	Clifford Wolf	2013-04-26
* \|	Fixed hierarchy pass for hierarchies of parametric modules	Clifford Wolf	2013-04-26
* \|	Only use sha1 checksums for names of parametric modules when the verbose form...	Clifford Wolf	2013-04-26
* \|	Fixed "show -format ..." command line parsing	Clifford Wolf	2013-04-15
* \|	Added "submod -name ..." support	Clifford Wolf	2013-04-15
* \|	Fixed a bug in AST frontend for cases with non-blocking assigned variables as...	Clifford Wolf	2013-04-13
* \|	Fixed a bug in opt_const when optimizing 1-bit compares with constants	Clifford Wolf	2013-04-13
* \|	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-04-07
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\| * \	Merge pull request #5 from hansiglaser/master	Clifford Wolf	2013-04-05
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\| \| * \|	fsm_export: optionally use binary state encoding as state names instead of	Johann Glaser	2013-04-05
\| * \| \|	Merge pull request #4 from hansiglaser/master	Clifford Wolf	2013-04-05
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\| \| * \|	fsm_export: specify KISS filename on command line	Johann Glaser	2013-04-05
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* / /	Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v	Clifford Wolf	2013-04-07
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* \|	Fixed/improved handling of colored wires in show command	Clifford Wolf	2013-04-01
* \|	Added support for @<set-name> in expand select ops (%x, %ci, %co)	Clifford Wolf	2013-04-01
* \|	Removed 4096 bytes limit for size of command from script file	Clifford Wolf	2013-04-01
* \|	Added -color <color> <selection> option to show command	Clifford Wolf	2013-04-01
* \|	Fixed "select" for "%%" stmt with emty stack	Clifford Wolf	2013-03-31
* \|	Added "script" command	Clifford Wolf	2013-03-31
* \|	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31
* \|	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31
* \|	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	Clifford Wolf	2013-03-31
* \|	Added k68 (m68k compatible cpu) test case from verilator	Clifford Wolf	2013-03-31
* \|	Improved opt_share for reduce cells	Clifford Wolf	2013-03-29
* \|	Improved opt_share for commutative standard cells	Clifford Wolf	2013-03-29
* \|	Added EXTRA_TARGETS Makefile variable	Clifford Wolf	2013-03-28
* \|	Improved Makefile: Added ENABLE_* switches	Clifford Wolf	2013-03-28
* \|	Implemented TCL support (only via -c option at the moment)	Clifford Wolf	2013-03-28