yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	New upstream version 0.9	Ruben Undheim	2019-10-18
*	Imported GIT HEAD: 0.8+20190328git32bd0f2	Ruben Undheim	2019-03-28
*	New upstream version 0.7+20181007git9850de4	Ruben Undheim	2018-10-15
*	New upstream version 0.7+20180830git0b7a184	Ruben Undheim	2018-08-30
*	Imported yosys 0.7	Ruben Undheim	2016-11-03
*	Squashed commit of the following:	Ruben Undheim	2016-09-23
*	Bugfixes in writing of memories as Verilog	Clifford Wolf	2015-09-25
*	Another block of spelling fixes	Larry Doolittle	2015-08-14
*	Re-created command-reference-manual.tex, copied some doc fixes to online help	Clifford Wolf	2015-08-14
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
*	$mem cell in verilog backend : grouped writes by clock	luke whittlesey	2015-06-08
*	Bug fix in $mem verilog backend + changed tests/bram flow of make test.	luke whittlesey	2015-06-04
*	Some fixes for $mem in verilog back-end	Clifford Wolf	2015-05-20
*	Merge pull request #63 from wluker/verilog-backend-mem	Clifford Wolf	2015-05-11
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\| *	Fixed bug in $mem cell verilog code generation.	luke whittlesey	2015-05-11
* \|	Disabled broken $mem support in verilog backend	Clifford Wolf	2015-05-10
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*	Made changes recommended by Clifford Wolf ...	luke whittlesey	2015-05-10
*	Verilog backend for $mem cells should now be able to handle different	luke whittlesey	2015-05-08
*	Added support for $mem cells in the verilog backend.	luke whittlesey	2015-05-07
*	Minor fixes in handling of "init" attribute	Clifford Wolf	2015-04-09
*	Added "init" attribute support to verilog backend	Clifford Wolf	2015-04-04
*	Added Verilog backend $dffsr support	Clifford Wolf	2015-03-18
*	Fixed "write_verilog -attr2comment" handling of "*/" in strings	Clifford Wolf	2015-02-13
*	Added dict/pool.sort()	Clifford Wolf	2015-01-24
*	Cosmetic changes in verilog output format	Clifford Wolf	2015-01-02
*	Replaced std::unordered_map as implementation for Yosys::dict	Clifford Wolf	2014-12-26
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26
*	Added $dffe support to write_verilog	Clifford Wolf	2014-12-20
*	Fixed generation of temp names in verilog backend	Clifford Wolf	2014-11-07
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
*	namespace Yosys	Clifford Wolf	2014-09-27
*	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
*	Using $pos models for $bu0	Clifford Wolf	2014-09-03
*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23
*	Fixed AOI/OAI expr handling in verilog backend	Clifford Wolf	2014-08-16
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...	Clifford Wolf	2014-08-16
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
*	Refactoring of CellType class	Clifford Wolf	2014-08-14
*	Be more conservative with printing decimal numbers in verilog backend	Clifford Wolf	2014-08-02
*	Improved verilog output for ordinary $mux cells	Clifford Wolf	2014-08-02
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26