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genrtlil.cc
Commit message (
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Author
Age
*
More fixes in ternary op sign handling
Clifford Wolf
2013-07-12
*
Fixed sign handling in ternary operator
Clifford Wolf
2013-07-12
*
Another vloghammer related bugfix
Clifford Wolf
2013-07-11
*
Fixed sign propagation in bit-wise operators
Clifford Wolf
2013-07-09
*
More fixes in ast expression sign/width handling
Clifford Wolf
2013-07-09
*
Major redesign of expr width/sign detecion (verilog/ast frontend)
Clifford Wolf
2013-07-09
*
Fixed another bug found using vloghammer
Clifford Wolf
2013-07-07
*
Added defparam support to Verilog/AST frontend
Clifford Wolf
2013-07-04
*
More fixes for bugs found using xsthammer
Clifford Wolf
2013-06-13
*
Sign-extension related fixes in SatGen and AST frontend
Clifford Wolf
2013-06-10
*
Fixes and improvements in AST const folding
Clifford Wolf
2013-06-10
*
Enabled AST/Verilog front-end optimizations per default
Clifford Wolf
2013-06-10
*
Fixed a bug in AST frontend for cases with non-blocking assigned variables as...
Clifford Wolf
2013-04-13
*
Now only use value from "initial" when no matching "always" block is found
Clifford Wolf
2013-03-31
*
Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
Clifford Wolf
2013-03-31
*
Fixed handling of unconditional generate blocks
Clifford Wolf
2013-03-26
*
Added nosync attribute and some async reset related fixes
Clifford Wolf
2013-03-25
*
Moved stand-alone libs to libs/ directory and added libs/subcircuit
Clifford Wolf
2013-02-27
*
initial import
Clifford Wolf
2013-01-05