yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	More fixes in ternary op sign handling	Clifford Wolf	2013-07-12
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*	Fixed sign handling in ternary operator	Clifford Wolf	2013-07-12
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*	Another vloghammer related bugfix	Clifford Wolf	2013-07-11
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*	Fixed sign propagation in bit-wise operators	Clifford Wolf	2013-07-09
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*	More fixes in ast expression sign/width handling	Clifford Wolf	2013-07-09
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*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09
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*	Fixed another bug found using vloghammer	Clifford Wolf	2013-07-07
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*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04
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*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13
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*	Sign-extension related fixes in SatGen and AST frontend	Clifford Wolf	2013-06-10
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*	Fixes and improvements in AST const folding	Clifford Wolf	2013-06-10
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*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10
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*	Fixed a bug in AST frontend for cases with non-blocking assigned variables ↵	Clifford Wolf	2013-04-13
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*	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31
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*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31
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*	Fixed handling of unconditional generate blocks	Clifford Wolf	2013-03-26
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*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25
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*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27
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*	initial import	Clifford Wolf	2013-01-05