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simplify.cc
Commit message (
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Author
Age
*
Added non-std verilog assume() statement
Clifford Wolf
2015-02-26
*
Added deep recursion warning to AST simplify
Clifford Wolf
2015-02-20
*
Parser support for complex delay expressions
Clifford Wolf
2015-02-20
*
Various fixes for memories with offsets
Clifford Wolf
2015-02-14
*
Added "read_verilog -nomeminit" and "nomeminit" attribute
Clifford Wolf
2015-02-14
*
Creating $meminit cells in verilog front-end
Clifford Wolf
2015-02-14
*
Added AstNode::simplify() recursion counter
Clifford Wolf
2015-02-13
*
Added ENABLE_NDEBUG makefile options
Clifford Wolf
2015-01-24
*
Ignoring more system task and functions
Clifford Wolf
2015-01-15
*
Fixed handling of "input foo; reg [0:0] foo;"
Clifford Wolf
2015-01-15
*
Consolidate "Blocking assignment to memory.." msgs for the same line
Clifford Wolf
2015-01-15
*
dict/pool changes in ast
Clifford Wolf
2014-12-29
*
Fixed mem2reg warning message
Clifford Wolf
2014-12-27
*
Added log_warning() API
Clifford Wolf
2014-11-09
*
AST simplifier: optimize constant AST_CASE nodes before recursively descending
Clifford Wolf
2014-10-29
*
Improvements in $readmem[bh] implementation
Clifford Wolf
2014-10-26
*
Added support for $readmemh/$readmemb
Clifford Wolf
2014-10-26
*
Fixed various VS warnings
Clifford Wolf
2014-10-18
*
Wrapped math in int constructor
William Speirs
2014-10-17
*
Fixed handling of invalid array access in mem2reg code
Clifford Wolf
2014-10-16
*
Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
*
Another $clog2 bugfix
Clifford Wolf
2014-09-08
*
Fixed $clog2 (off by one error)
Clifford Wolf
2014-09-06
*
Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
*
Fixed small memory leak in ast simplify
Clifford Wolf
2014-08-21
*
Added support for DPI function with different names in C and Verilog
Clifford Wolf
2014-08-21
*
Fixed memory leak in DPI function calls
Clifford Wolf
2014-08-21
*
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
Clifford Wolf
2014-08-21
*
Added "via_celltype" attribute on task/func
Clifford Wolf
2014-08-18
*
Added const folding of AST_CASE to AST simplifier
Clifford Wolf
2014-08-18
*
Fixed handling of task outputs
Clifford Wolf
2014-08-14
*
Added AST_MULTIRANGE (arrays with more than 1 dimension)
Clifford Wolf
2014-08-06
*
Improved scope resolution of local regs in Verilog+AST frontend
Clifford Wolf
2014-08-05
*
Fixed AST handling of variables declared inside a functions main block
Clifford Wolf
2014-08-05
*
More bugfixes related to new RTLIL::IdString
Clifford Wolf
2014-08-02
*
Preparations for RTLIL::IdString redesign: cleanup of existing code
Clifford Wolf
2014-08-02
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
*
Removed left over debug code
Clifford Wolf
2014-07-28
*
Fixed part selects of parameters
Clifford Wolf
2014-07-28
*
Added support for "upto" wires to Verilog front- and back-end
Clifford Wolf
2014-07-28
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
*
Fixed two memory leaks in ast simplify
Clifford Wolf
2014-07-25
*
Various small fixes (from gcc compiler warnings)
Clifford Wolf
2014-07-23
*
Implemented dynamic bit-/part-select for memory writes
Clifford Wolf
2014-07-17
*
Added support for bit/part select to mem2reg rewriter
Clifford Wolf
2014-07-17
*
Added support for constant bit- or part-select for memory writes
Clifford Wolf
2014-07-17
*
changes in verilog frontend for new $mem/$memwr WR_EN interface
Clifford Wolf
2014-07-16
*
Fixed processing of initial values for block-local variables
Clifford Wolf
2014-07-11
*
Fixed handling of mixed real/int ternary expressions
Clifford Wolf
2014-06-25
*
Added AstNode::MEM2REG_FL_CMPLX_LHS
Clifford Wolf
2014-06-17
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