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Author
Age
*
Import more std:: stuff into Yosys namespace
Clifford Wolf
2015-10-25
*
Fixed complexity of assigning to vectors in constant functions
Clifford Wolf
2015-10-01
*
Fixed detection of unconditional $readmem[hb]
Clifford Wolf
2015-09-30
*
Bugfixes in $readmem[hb]
Clifford Wolf
2015-09-25
*
Fixed segfault in AstNode::asReal
Clifford Wolf
2015-09-25
*
Added read-enable to memory model
Clifford Wolf
2015-09-25
*
Fixed AstNode::mkconst_bits() segfault on zero-sized constant
Clifford Wolf
2015-09-24
*
Bugfix in handling of multi-dimensional memories
Clifford Wolf
2015-09-23
*
Warning for $display/$write outside initial block
Clifford Wolf
2015-09-23
*
Fixed multi-level prefix resolving
Clifford Wolf
2015-09-22
*
Improvements to $display system task
Andrew Zonenberg
2015-09-19
*
Added AST_INITIAL checks for $finish and $display
Clifford Wolf
2015-09-18
*
Initial implementation of $display()
Andrew Zonenberg
2015-09-18
*
Initial implementation of $finish()
Andrew Zonenberg
2015-09-18
*
Fixed handling of memory read without address
Clifford Wolf
2015-08-22
*
Another block of spelling fixes
Larry Doolittle
2015-08-14
*
Keep gcc from complaining about uninitialized variables
Larry Doolittle
2015-08-14
*
Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
*
Added WORDS parameter to $meminit
Clifford Wolf
2015-07-31
*
Fixed nested mem2reg
Clifford Wolf
2015-07-29
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
*
Fixed handling of parameters with reversed range
Clifford Wolf
2015-06-08
*
Fixed signedness of genvar expressions
Clifford Wolf
2015-05-29
*
Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()
Clifford Wolf
2015-03-01
*
Added non-std verilog assume() statement
Clifford Wolf
2015-02-26
*
Added deep recursion warning to AST simplify
Clifford Wolf
2015-02-20
*
Parser support for complex delay expressions
Clifford Wolf
2015-02-20
*
Convert floating point cell parameters to strings
Clifford Wolf
2015-02-18
*
Various fixes for memories with offsets
Clifford Wolf
2015-02-14
*
Added "read_verilog -nomeminit" and "nomeminit" attribute
Clifford Wolf
2015-02-14
*
Creating $meminit cells in verilog front-end
Clifford Wolf
2015-02-14
*
Added AstNode::simplify() recursion counter
Clifford Wolf
2015-02-13
*
Ignore explicit assignments to constants in HDL code
Clifford Wolf
2015-02-08
*
Fixed a bug with autowire bit size
Clifford Wolf
2015-02-08
*
Added ENABLE_NDEBUG makefile options
Clifford Wolf
2015-01-24
*
Ignoring more system task and functions
Clifford Wolf
2015-01-15
*
Fixed handling of "input foo; reg [0:0] foo;"
Clifford Wolf
2015-01-15
*
Consolidate "Blocking assignment to memory.." msgs for the same line
Clifford Wolf
2015-01-15
*
Fixed memory->start_offset handling
Clifford Wolf
2015-01-01
*
Added global yosys_celltypes
Clifford Wolf
2014-12-29
*
dict/pool changes in ast
Clifford Wolf
2014-12-29
*
Changed more code to dict<> and pool<>
Clifford Wolf
2014-12-28
*
Fixed mem2reg warning message
Clifford Wolf
2014-12-27
*
Added Yosys::{dict,nodict,vector} container types
Clifford Wolf
2014-12-26
*
Renamed extend() to extend_xx(), changed most users to extend_u0()
Clifford Wolf
2014-12-24
*
Added log_warning() API
Clifford Wolf
2014-11-09
*
AST simplifier: optimize constant AST_CASE nodes before recursively descending
Clifford Wolf
2014-10-29
*
Improvements in $readmem[bh] implementation
Clifford Wolf
2014-10-26
*
Added support for $readmemh/$readmemb
Clifford Wolf
2014-10-26
*
Fixed constant "cond ? string1 : string2" with strings of different size
Clifford Wolf
2014-10-25
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