index
:
yosys
master
Debian dgit repo for package yosys
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
frontends
/
verilog
/
verilog_frontend.cc
Commit message (
Expand
)
Author
Age
*
Added read_verilog -setattr
Clifford Wolf
2014-02-05
*
Added support for blanks after -I and -D in read_verilog
Clifford Wolf
2014-02-02
*
Added read_verilog -icells option
Clifford Wolf
2014-01-29
*
Added verilog_defaults command
Clifford Wolf
2014-01-17
*
Added verilog frontend -ignore_redef option
Clifford Wolf
2013-11-24
*
Renamed "placeholder" to "blackbox"
Clifford Wolf
2013-11-22
*
Enable {* .. *} feature per default (removes dependency to REJECT feature in ...
Clifford Wolf
2013-11-22
*
Added support for include directories with the new '-I' argument of the
Johann Glaser
2013-08-20
*
Improved ast dumping (ast/verilog frontend)
Clifford Wolf
2013-08-19
*
Enabled AST/Verilog front-end optimizations per default
Clifford Wolf
2013-06-10
*
added option '-Dname[=definition]' to command 'read_verilog'
Johann Glaser
2013-05-19
*
Implemented proper handling of stub placeholder modules
Clifford Wolf
2013-03-28
*
Added mem2reg option to verilog frontend
Clifford Wolf
2013-03-24
*
Added help messages to ilang and verilog frontends
Clifford Wolf
2013-03-01
*
Moved stand-alone libs to libs/ directory and added libs/subcircuit
Clifford Wolf
2013-02-27
*
initial import
Clifford Wolf
2013-01-05