summaryrefslogtreecommitdiff
path: root/frontends/verilog/verilog_lexer.l
Commit message (Expand)AuthorAge
* New upstream version 0.9Ruben Undheim2019-10-18
* Imported GIT HEAD: 0.8+20190328git32bd0f2Ruben Undheim2019-03-28
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Squashed commit of the following:Ruben Undheim2016-09-23
* SystemVerilog also has assume(), added implicit -D FORMALClifford Wolf2015-10-13
* Fixed support for $write system taskClifford Wolf2015-09-23
* Another block of spelling fixesLarry Doolittle2015-08-14
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-12
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Ignore celldefine directive in verilog front-endClifford Wolf2015-03-25
* Added non-std verilog assume() statementClifford Wolf2015-02-26
* Fixed handling of "//" in filenames in verilog pre-processorClifford Wolf2015-02-14
* Ignoring more system task and functionsClifford Wolf2015-01-15
* Improved some warning messagesClifford Wolf2014-12-27
* Fixed minor bug in parsing delaysClifford Wolf2014-11-24
* Fixed two minor bugs in constant parsingClifford Wolf2014-11-24
* Added log_warning() APIClifford Wolf2014-11-09
* Re-introduced Yosys::readsome() helper functionClifford Wolf2014-10-23
* Updated lexers & parsers to include prefixesWilliam Speirs2014-10-15