index
:
yosys
master
Debian dgit repo for package yosys
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
frontends
/
verilog
/
verilog_lexer.l
Commit message (
Expand
)
Author
Age
*
New upstream version 0.9
Ruben Undheim
2019-10-18
*
Imported GIT HEAD: 0.8+20190328git32bd0f2
Ruben Undheim
2019-03-28
*
New upstream version 0.7+20180830git0b7a184
Ruben Undheim
2018-08-30
*
Squashed commit of the following:
Ruben Undheim
2016-09-23
*
SystemVerilog also has assume(), added implicit -D FORMAL
Clifford Wolf
2015-10-13
*
Fixed support for $write system task
Clifford Wolf
2015-09-23
*
Another block of spelling fixes
Larry Doolittle
2015-08-14
*
Adjust makefiles to work with out-of-tree builds
Clifford Wolf
2015-08-12
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
*
Ignore celldefine directive in verilog front-end
Clifford Wolf
2015-03-25
*
Added non-std verilog assume() statement
Clifford Wolf
2015-02-26
*
Fixed handling of "//" in filenames in verilog pre-processor
Clifford Wolf
2015-02-14
*
Ignoring more system task and functions
Clifford Wolf
2015-01-15
*
Improved some warning messages
Clifford Wolf
2014-12-27
*
Fixed minor bug in parsing delays
Clifford Wolf
2014-11-24
*
Fixed two minor bugs in constant parsing
Clifford Wolf
2014-11-24
*
Added log_warning() API
Clifford Wolf
2014-11-09
*
Re-introduced Yosys::readsome() helper function
Clifford Wolf
2014-10-23
*
Updated lexers & parsers to include prefixes
William Speirs
2014-10-15