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Author
Age
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Fixes for early width and sign detection in ast simplifier
Clifford Wolf
2013-11-04
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further improved early width and sign detection in ast simplifier
Clifford Wolf
2013-11-04
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Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT
Clifford Wolf
2013-11-03
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Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing ↵
Clifford Wolf
2013-11-02
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before constfold fixes)
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Various ast changes for early expression width detection (prep for constfold ↵
Clifford Wolf
2013-11-02
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fixes)
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Fixed handling of boolean attributes (frontends)
Clifford Wolf
2013-10-24
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Fixed handling of boolean attributes (kernel)
Clifford Wolf
2013-10-24
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Fixed parsing of value-less attributes in ilang
Clifford Wolf
2013-10-23
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fixed Verilog parser filename and line numbering issue with include files
Johann Glaser
2013-08-21
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Added support for include directories with the new '-I' argument of the
Johann Glaser
2013-08-20
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'read_verilog' command
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Added support for notif0/notif1 primitives
Johann Glaser
2013-08-20
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Fixed width and sign detection for ** operator
Clifford Wolf
2013-08-19
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Added support for bufif0/bufif1 primitives
Clifford Wolf
2013-08-19
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Improved ast dumping (ast/verilog frontend)
Clifford Wolf
2013-08-19
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Added support for "2**n" shifter encoding
Clifford Wolf
2013-08-12
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Added $div and $mod technology mapping
Clifford Wolf
2013-08-09
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Added "design" command (-reset, -save, -load)
Clifford Wolf
2013-07-27
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More fixes in ternary op sign handling
Clifford Wolf
2013-07-12
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Fixed sign handling in ternary operator
Clifford Wolf
2013-07-12
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Another vloghammer related bugfix
Clifford Wolf
2013-07-11
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Fixed sign propagation in bit-wise operators
Clifford Wolf
2013-07-09
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More fixes in ast expression sign/width handling
Clifford Wolf
2013-07-09
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Major redesign of expr width/sign detecion (verilog/ast frontend)
Clifford Wolf
2013-07-09
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Fixed another bug found using vloghammer
Clifford Wolf
2013-07-07
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Fixed AST_CONSTANT node generation
Clifford Wolf
2013-07-07
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Added defparam support to Verilog/AST frontend
Clifford Wolf
2013-07-04
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More fixes for bugs found using xsthammer
Clifford Wolf
2013-06-13
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Further improved and extended xsthammer
Clifford Wolf
2013-06-11
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Sign-extension related fixes in SatGen and AST frontend
Clifford Wolf
2013-06-10
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Fixes and improvements in AST const folding
Clifford Wolf
2013-06-10
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Enabled AST/Verilog front-end optimizations per default
Clifford Wolf
2013-06-10
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Added SAT generator and simple sat_solve command
Clifford Wolf
2013-06-07
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Added log_assert() api
Clifford Wolf
2013-05-24
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Fixed memory leak in ilang frontend
Clifford Wolf
2013-05-23
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added option '-Dname[=definition]' to command 'read_verilog'
Johann Glaser
2013-05-19
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Merge branch 'bugfix'
Clifford Wolf
2013-05-16
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Fixed synthesis of functions in latched blocks
Clifford Wolf
2013-05-16
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Added support for verilog === operator
Clifford Wolf
2013-05-07
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Fixed handling of positional module parameters
Clifford Wolf
2013-04-26
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Only use sha1 checksums for names of parametric modules when the verbose ↵
Clifford Wolf
2013-04-26
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form is to long
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Fixed a bug in AST frontend for cases with non-blocking assigned variables ↵
Clifford Wolf
2013-04-13
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as case values
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Now only use value from "initial" when no matching "always" block is found
Clifford Wolf
2013-03-31
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Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
Clifford Wolf
2013-03-31
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Implemented proper handling of stub placeholder modules
Clifford Wolf
2013-03-28
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Improvements and bugfixes for generate blocks with local signals
Clifford Wolf
2013-03-26
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Fixed handling of unconditional generate blocks
Clifford Wolf
2013-03-26
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Added nosync attribute and some async reset related fixes
Clifford Wolf
2013-03-25
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Added mem2reg option to verilog frontend
Clifford Wolf
2013-03-24
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Another fix in mem2reg ast simplify logic
Clifford Wolf
2013-03-24
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Improved mem2reg handling in ast simplifier
Clifford Wolf
2013-03-24
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