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Author
Age
*
Added deep recursion warning to AST simplify
Clifford Wolf
2015-02-20
*
Parser support for complex delay expressions
Clifford Wolf
2015-02-20
*
YosysJS stuff
Clifford Wolf
2015-02-19
*
Convert floating point cell parameters to strings
Clifford Wolf
2015-02-18
*
Various fixes for memories with offsets
Clifford Wolf
2015-02-14
*
Added "read_verilog -nomeminit" and "nomeminit" attribute
Clifford Wolf
2015-02-14
*
Creating $meminit cells in verilog front-end
Clifford Wolf
2015-02-14
*
Fixed handling of "//" in filenames in verilog pre-processor
Clifford Wolf
2015-02-14
*
Added AstNode::simplify() recursion counter
Clifford Wolf
2015-02-13
*
Improved read_verilog support for empty behavioral statements
Clifford Wolf
2015-02-10
*
Ignore explicit assignments to constants in HDL code
Clifford Wolf
2015-02-08
*
Fixed a bug with autowire bit size
Clifford Wolf
2015-02-08
*
Added ENABLE_NDEBUG makefile options
Clifford Wolf
2015-01-24
*
Ignoring more system task and functions
Clifford Wolf
2015-01-15
*
Fixed handling of "input foo; reg [0:0] foo;"
Clifford Wolf
2015-01-15
*
Consolidate "Blocking assignment to memory.." msgs for the same line
Clifford Wolf
2015-01-15
*
Enable bison to be customized
Fabio Utzig
2015-01-08
*
Define YOSYS and SYNTHESIS in preproc
Clifford Wolf
2015-01-02
*
Fixed memory->start_offset handling
Clifford Wolf
2015-01-01
*
Added global yosys_celltypes
Clifford Wolf
2014-12-29
*
dict/pool changes in ast
Clifford Wolf
2014-12-29
*
Changed more code to dict<> and pool<>
Clifford Wolf
2014-12-28
*
Improved some warning messages
Clifford Wolf
2014-12-27
*
Fixed mem2reg warning message
Clifford Wolf
2014-12-27
*
Added Yosys::{dict,nodict,vector} container types
Clifford Wolf
2014-12-26
*
Renamed extend() to extend_xx(), changed most users to extend_u0()
Clifford Wolf
2014-12-24
*
Fixed supply0/supply1 with many wires
Clifford Wolf
2014-12-11
*
Fixed minor bug in parsing delays
Clifford Wolf
2014-11-24
*
Fixed two minor bugs in constant parsing
Clifford Wolf
2014-11-24
*
Added warning for use of 'z' constants in HDL
Clifford Wolf
2014-11-14
*
Fixed parsing of nested verilog concatenation and replicate
Clifford Wolf
2014-11-12
*
Added log_warning() API
Clifford Wolf
2014-11-09
*
Added "ENABLE_PLUGINS := 0" to verific amd64 build instructions
Clifford Wolf
2014-11-08
*
Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."
Clifford Wolf
2014-10-30
*
AST simplifier: optimize constant AST_CASE nodes before recursively descending
Clifford Wolf
2014-10-29
*
Added support for task and function args in parentheses
Clifford Wolf
2014-10-27
*
Improvements in $readmem[bh] implementation
Clifford Wolf
2014-10-26
*
Added support for $readmemh/$readmemb
Clifford Wolf
2014-10-26
*
Fixed constant "cond ? string1 : string2" with strings of different size
Clifford Wolf
2014-10-25
*
Re-introduced Yosys::readsome() helper function
Clifford Wolf
2014-10-23
*
minor indenting corrections
Clifford Wolf
2014-10-19
*
Builds on Mac 10.9.2 with LLVM 3.5.
Parviz Palangpour
2014-10-19
*
Fixed various VS warnings
Clifford Wolf
2014-10-18
*
Header changes so it will compile on VS
William Speirs
2014-10-17
*
Wrapped math in int constructor
William Speirs
2014-10-17
*
Print "SystemVerilog" in "read_verilog -sv" log messages
Clifford Wolf
2014-10-16
*
Fixed handling of invalid array access in mem2reg code
Clifford Wolf
2014-10-16
*
Updated .gitignore file for ilang and verilog frontends
Clifford Wolf
2014-10-15
*
Replaced readsome() with read() and gcount()
Clifford Wolf
2014-10-15
*
Updated lexers & parsers to include prefixes
William Speirs
2014-10-15
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