yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added global yosys_celltypes	Clifford Wolf	2014-12-29
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*	Changed more code to dict<> and pool<>	Clifford Wolf	2014-12-28
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*	Added functionality to dff2dffe pass	Clifford Wolf	2014-12-08
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*	Added $_DFFE_??_ cell types	Clifford Wolf	2014-12-08
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*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
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*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03
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*	Added $lcu cell type	Clifford Wolf	2014-09-08
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*	Added "$fa" cell type	Clifford Wolf	2014-09-08
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*	Added $macc cell type	Clifford Wolf	2014-09-06
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*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
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*	Added eval model for $lut cells	Clifford Wolf	2014-08-31
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*	Added $alu cell type	Clifford Wolf	2014-08-30
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*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22
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*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵	Clifford Wolf	2014-08-16
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*	Added CellTypes::cell_evaluable()	Clifford Wolf	2014-08-16
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*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15
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*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
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*	Added module->ports	Clifford Wolf	2014-08-14
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*	Refactoring of CellType class	Clifford Wolf	2014-08-14
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*	RIP $safe_pmux	Clifford Wolf	2014-08-14
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*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
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*	Added support for dlatchsr cells	Clifford Wolf	2014-03-31
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*	Fixed const folding of $bu0 cells	Clifford Wolf	2014-02-27
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*	Added $slice and $concat to CellTypes list	Clifford Wolf	2014-02-07
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*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07
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*	Added $assert cell	Clifford Wolf	2014-01-19
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*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28
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*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
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*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18
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*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18
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*	Added $lut cells and abc lut mapping support	Clifford Wolf	2013-07-23
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*	Fixed even more ConstEval bugs found using xsthammer	Clifford Wolf	2013-06-14
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*	Added consteval testing to xsthammer and fixed bugs	Clifford Wolf	2013-06-13
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*	Added log_assert() api	Clifford Wolf	2013-05-24
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*	Added additional functionality and cleanups in sigtools.h and celltypes.h	Clifford Wolf	2013-03-15
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*	Added #ci and #co selection operators	Clifford Wolf	2013-03-14
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*	Added $sr cell type to celltypes.h	Clifford Wolf	2013-03-14
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*	Added library support to celltypes class and show pass	Clifford Wolf	2013-03-03
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*	initial import	Clifford Wolf	2013-01-05