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rtlil.cc
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Author
Age
*
Added $eq/$neq -> $logic_not/$reduce_bool optimization
Clifford Wolf
2015-04-29
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Improved attributes API and handling of "src" attributes
Clifford Wolf
2015-04-24
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Avoid parameter values with size 0 ($mem cells)
Clifford Wolf
2015-04-05
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Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types
Clifford Wolf
2015-04-05
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Added $assume cell type
Clifford Wolf
2015-02-26
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Added $meminit support to "memory" command
Clifford Wolf
2015-02-14
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Added $meminit cell type
Clifford Wolf
2015-02-14
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Added SigSpec::has_const()
Clifford Wolf
2015-02-08
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Added cell->known(), cell->input(portname), cell->output(portname)
Clifford Wolf
2015-02-07
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Skip blackbox modules in design->selected_modules()
Clifford Wolf
2015-02-03
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Added "equiv_make -blacklist <file> -encfile <file>"
Clifford Wolf
2015-01-31
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Added dict/pool.sort()
Clifford Wolf
2015-01-24
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Progress in equiv_simple
Clifford Wolf
2015-01-21
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Added equiv_make command
Clifford Wolf
2015-01-19
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Added $equiv cell type
Clifford Wolf
2015-01-19
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Optimizing no-op cell->setPort()
Clifford Wolf
2015-01-17
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Removed SigSpec::extend_xx() api
Clifford Wolf
2015-01-01
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added hashlib::mkhash_init
Clifford Wolf
2014-12-30
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Added "yosys -X"
Clifford Wolf
2014-12-29
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Added mkhash_xorshift()
Clifford Wolf
2014-12-29
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Added memhasher (yosys -M)
Clifford Wolf
2014-12-28
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Fixed performance bug in object hashing
Clifford Wolf
2014-12-28
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Renamed hashmap.h to hashlib.h, some related improvements
Clifford Wolf
2014-12-28
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More dict/pool related changes
Clifford Wolf
2014-12-27
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More hashtable finetuning
Clifford Wolf
2014-12-27
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Replaced std::unordered_set (nodict) with Yosys::pool
Clifford Wolf
2014-12-26
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Replaced std::unordered_map as implementation for Yosys::dict
Clifford Wolf
2014-12-26
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Added new_dict (hashmap.h) and re-enabled code coverage counters
Clifford Wolf
2014-12-26
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Added Yosys::{dict,nodict,vector} container types
Clifford Wolf
2014-12-26
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Renamed extend() to extend_xx(), changed most users to extend_u0()
Clifford Wolf
2014-12-24
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Added IdString::destruct_guard hack
Clifford Wolf
2014-12-11
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Added bool constructors to SigBit and SigSpec
Clifford Wolf
2014-12-08
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Added module->addDffe() and module->addDffeGate()
Clifford Wolf
2014-12-08
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Added $dffe cell type
Clifford Wolf
2014-12-08
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Added $_DFFE_??_ cell types
Clifford Wolf
2014-12-08
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Added log_warning() API
Clifford Wolf
2014-11-09
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Added support for $readmemh/$readmemb
Clifford Wolf
2014-10-26
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Fixed various VS warnings
Clifford Wolf
2014-10-18
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Various win32 / vs build fixes
Clifford Wolf
2014-10-17
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Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selects
Clifford Wolf
2014-10-16
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Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
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Added $_BUF_ cell type
Clifford Wolf
2014-10-03
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Initialize RTLIL::Const from std::vector<bool>
Clifford Wolf
2014-09-19
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Fixed monitor notifications for removed cell
Clifford Wolf
2014-09-14
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Added $lcu cell type
Clifford Wolf
2014-09-08
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Added "$fa" cell type
Clifford Wolf
2014-09-08
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Added $macc cell type
Clifford Wolf
2014-09-06
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Removed $bu0 cell type
Clifford Wolf
2014-09-04
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Create a default selection stack in RTLIL::Design::Design()
Clifford Wolf
2014-09-02
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Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵
Clifford Wolf
2014-09-01
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RTLIL::SigChunk::data
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