| Commit message (Expand) | Author | Age |
|---|
| * | Added RTLIL::Design::modules() | Clifford Wolf | 2014-07-27 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 |
| * | Added conversion from ObjRange to std::vector and std::set | Clifford Wolf | 2014-07-27 |
| * | Added RTLIL::ObjIterator and RTLIL::ObjRange | Clifford Wolf | 2014-07-27 |
| * | Using std::move() in SigSpec move constructor | Clifford Wolf | 2014-07-27 |
| * | Added RTLIL::SigSpec move constructor and move assignment operator | Clifford Wolf | 2014-07-27 |
| * | Mostly cosmetic changes to rtlil.h | Clifford Wolf | 2014-07-27 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 |
| * | Changed more code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 |
| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 |
| * | Added RTLIL::Cell::has(portname) | Clifford Wolf | 2014-07-26 |
| * | Added some missing "const" in rtlil.h | Clifford Wolf | 2014-07-26 |
| * | Added RTLIL::Module::connections() | Clifford Wolf | 2014-07-26 |
| * | Added RTLIL::Module::connect(const RTLIL::SigSig&) | Clifford Wolf | 2014-07-26 |
| * | Automatically pack SigSpec on copy/assign | Clifford Wolf | 2014-07-26 |
| * | Added new RTLIL::Cell port access methods | Clifford Wolf | 2014-07-26 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 |
| * | Added copy-constructor-like module->addCell(name, other) method | Clifford Wolf | 2014-07-26 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 |
| * | Added RTLIL::SigSpec is_chunk()/as_chunk() API | Clifford Wolf | 2014-07-25 |
| * | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 |
| * | Small changes regarding cover() and check() in SigSpec | Clifford Wolf | 2014-07-24 |
| * | Added hashing to RTLIL::SigSpec relational and equal operators | Clifford Wolf | 2014-07-23 |
| * | Added RTLIL::SigSpec::repeat() | Clifford Wolf | 2014-07-23 |
| * | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 |
| * | Removed RTLIL::SigSpec::expand() method | Clifford Wolf | 2014-07-23 |
| * | Fixed all users of SigSpec::chunks_rw() and removed it | Clifford Wolf | 2014-07-23 |
| * | Replaced RTLIL::SigSpec::operator!=() with inline version | Clifford Wolf | 2014-07-23 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 | Clifford Wolf | 2014-07-23 |
| * | Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&) | Clifford Wolf | 2014-07-23 |
| * | SigSpec refactoring: Added RTLIL::SigSpecIterator | Clifford Wolf | 2014-07-22 |
| * | SigSpec refactoring: added RTLIL::SigSpec::operator[] | Clifford Wolf | 2014-07-22 |
| * | Removed RTLIL::SigChunk::compare() | Clifford Wolf | 2014-07-22 |
| * | SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api | Clifford Wolf | 2014-07-22 |
| * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 |
| * | SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only | Clifford Wolf | 2014-07-22 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 |
| * | SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and ad... | Clifford Wolf | 2014-07-22 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 |
| * | Replaced depricated NEW_WIRE macro with module->addWire() calls | Clifford Wolf | 2014-07-21 |
| * | Removed deprecated module->new_wire() | Clifford Wolf | 2014-07-21 |
| * | Added module->remove(), module->addWire(), module->addCell(), cell->check() | Clifford Wolf | 2014-07-21 |
| * | Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion | Clifford Wolf | 2014-07-20 |
| * | Added SIZE() macro | Clifford Wolf | 2014-07-20 |
| * | Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit> | Clifford Wolf | 2014-07-18 |
| * | Added function-like cell creation helpers | Clifford Wolf | 2014-07-18 |
| * | Added support for dlatchsr cells | Clifford Wolf | 2014-03-31 |
| * | Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API | Clifford Wolf | 2014-03-15 |
