| Commit message (Expand) | Author | Age |
* | Added "dffinit", Support for initialized Xilinx DFF | Clifford Wolf | 2015-04-04 |
* | Some cleanups in "clean" | Clifford Wolf | 2015-02-24 |
* | Added SigSpec::has_const() | Clifford Wolf | 2015-02-08 |
* | Added cell->known(), cell->input(portname), cell->output(portname) | Clifford Wolf | 2015-02-07 |
* | Added "equiv_make -blacklist <file> -encfile <file>" | Clifford Wolf | 2015-01-31 |
* | Synced RTLIL::unescape_id() to log_id() behavior | Clifford Wolf | 2015-01-30 |
* | Added dict/pool.sort() | Clifford Wolf | 2015-01-24 |
* | Added equiv_make command | Clifford Wolf | 2015-01-19 |
* | Removed SigSpec::extend_xx() api | Clifford Wolf | 2015-01-01 |
* | Progress in memory_bram | Clifford Wolf | 2014-12-31 |
* | IdString optimization | Clifford Wolf | 2014-12-31 |
* | added hashlib::mkhash_init | Clifford Wolf | 2014-12-30 |
* | Added "yosys -X" | Clifford Wolf | 2014-12-29 |
* | Converting "share" to dict<> and pool<> complete | Clifford Wolf | 2014-12-29 |
* | Added mkhash_xorshift() | Clifford Wolf | 2014-12-29 |
* | Fixed performance bug in object hashing | Clifford Wolf | 2014-12-28 |
* | Renamed hashmap.h to hashlib.h, some related improvements | Clifford Wolf | 2014-12-28 |
* | More dict/pool related changes | Clifford Wolf | 2014-12-27 |
* | More hashtable finetuning | Clifford Wolf | 2014-12-27 |
* | Replaced std::unordered_set (nodict) with Yosys::pool | Clifford Wolf | 2014-12-26 |
* | Replaced std::unordered_map as implementation for Yosys::dict | Clifford Wolf | 2014-12-26 |
* | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 |
* | Renamed extend() to extend_xx(), changed most users to extend_u0() | Clifford Wolf | 2014-12-24 |
* | Added support for multiple clock domains to "abc" pass | Clifford Wolf | 2014-12-21 |
* | Fixed build with gcc 4.6 | Clifford Wolf | 2014-12-16 |
* | Added IdString::destruct_guard hack | Clifford Wolf | 2014-12-11 |
* | Added bool constructors to SigBit and SigSpec | Clifford Wolf | 2014-12-08 |
* | Added module->addDffe() and module->addDffeGate() | Clifford Wolf | 2014-12-08 |
* | Improved TopoSort determinism | Clifford Wolf | 2014-11-07 |
* | Fixed a few VS warnings | Clifford Wolf | 2014-10-17 |
* | Made iterators extend std::iterator and added == operator | William Speirs | 2014-10-15 |
* | Added support for "keep" on modules | Clifford Wolf | 2014-09-29 |
* | Initialize RTLIL::Const from std::vector<bool> | Clifford Wolf | 2014-09-19 |
* | Removed $bu0 cell type | Clifford Wolf | 2014-09-04 |
* | Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::... | Clifford Wolf | 2014-09-01 |
* | Added RTLIL::Const::size() | Clifford Wolf | 2014-08-31 |
* | Typo fixes in cell->*Param() API | Clifford Wolf | 2014-08-31 |
* | Added design->scratchpad | Clifford Wolf | 2014-08-30 |
* | Added is_signed argument to SigSpec.as_int() and Const.as_int() | Clifford Wolf | 2014-08-24 |
* | Added emscripten (emcc) support to build system and some build fixes | Clifford Wolf | 2014-08-22 |
* | Added mod->addGate() methods for new gate types | Clifford Wolf | 2014-08-19 |
* | Added module->uniquify() | Clifford Wolf | 2014-08-16 |
* | Renamed $_INV_ cell type to $_NOT_ | Clifford Wolf | 2014-08-15 |
* | More idstring sort_by_* helpers and fixed tpl ordering in techmap | Clifford Wolf | 2014-08-15 |
* | Added RTLIL::SigSpec::to_sigbit_map() | Clifford Wolf | 2014-08-14 |
* | Added sig.{replace,remove,extract} variants for std::{map,set} pattern | Clifford Wolf | 2014-08-14 |
* | Added module->ports | Clifford Wolf | 2014-08-14 |
* | RIP $safe_pmux | Clifford Wolf | 2014-08-14 |
* | Fixed SigBit(RTLIL::Wire *wire) constructor | Clifford Wolf | 2014-08-12 |
* | Added support for truncating of wires to wreduce pass | Clifford Wolf | 2014-08-05 |