| Commit message (Expand) | Author | Age |
* | Fixed proc_{self,share}_dirname error handling | Clifford Wolf | 2014-08-17 |
* | Improved sig.remove2() performance | Clifford Wolf | 2014-08-17 |
* | Added stackmap<> container | Clifford Wolf | 2014-08-17 |
* | Renamed toposort.h to utils.h | Clifford Wolf | 2014-08-17 |
* | Added module->uniquify() | Clifford Wolf | 2014-08-16 |
* | Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $... | Clifford Wolf | 2014-08-16 |
* | Added CellTypes::cell_evaluable() | Clifford Wolf | 2014-08-16 |
* | Added log_spacer() | Clifford Wolf | 2014-08-16 |
* | Renamed $lut ports to follow A-Y naming scheme | Clifford Wolf | 2014-08-15 |
* | Renamed $_INV_ cell type to $_NOT_ | Clifford Wolf | 2014-08-15 |
* | More idstring sort_by_* helpers and fixed tpl ordering in techmap | Clifford Wolf | 2014-08-15 |
* | Added Frontend "+/" filename syntax for files from proc_share_dir | Clifford Wolf | 2014-08-15 |
* | Added RTLIL::SigSpec::to_sigbit_map() | Clifford Wolf | 2014-08-14 |
* | Added sig.{replace,remove,extract} variants for std::{map,set} pattern | Clifford Wolf | 2014-08-14 |
* | Added module->ports | Clifford Wolf | 2014-08-14 |
* | Refactoring of CellType class | Clifford Wolf | 2014-08-14 |
* | RIP $safe_pmux | Clifford Wolf | 2014-08-14 |
* | Fixed SigBit(RTLIL::Wire *wire) constructor | Clifford Wolf | 2014-08-12 |
* | Another build fix by americanrouter (via reddit) | Clifford Wolf | 2014-08-11 |
* | Fixed build with gcc-4.6 | Clifford Wolf | 2014-08-07 |
* | Added support for truncating of wires to wreduce pass | Clifford Wolf | 2014-08-05 |
* | Added RTLIL::IdString::in(...) | Clifford Wolf | 2014-08-04 |
* | Added query() API to ModIndex | Clifford Wolf | 2014-08-03 |
* | Added ID() macro for static IdStrings | Clifford Wolf | 2014-08-03 |
* | Fixed a va_list corruption in logv_error() | Clifford Wolf | 2014-08-02 |
* | Bugfix in "techmap -extern" | Clifford Wolf | 2014-08-02 |
* | Removed at() method from RTLIL::IdString | Clifford Wolf | 2014-08-02 |
* | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 |
* | More bugfixes related to new RTLIL::IdString | Clifford Wolf | 2014-08-02 |
* | Limit size of log_signal buffer to 100 elements | Clifford Wolf | 2014-08-02 |
* | Improvements in new RTLIL::IdString implementation | Clifford Wolf | 2014-08-02 |
* | Implemented new reference counting RTLIL::IdString | Clifford Wolf | 2014-08-02 |
* | Fixed memory corruption related to id2cstr() | Clifford Wolf | 2014-08-02 |
* | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 |
* | Preparations for RTLIL::IdString redesign: cleanup of existing code | Clifford Wolf | 2014-08-02 |
* | Added logfile hash to statistics footer | Clifford Wolf | 2014-08-01 |
* | Added per-pass cpu usage statistics | Clifford Wolf | 2014-08-01 |
* | Added ModIndex helper class, some changes to RTLIL::Monitor | Clifford Wolf | 2014-08-01 |
* | Packed SigBit::data and SigBit::offset in a union | Clifford Wolf | 2014-08-01 |
* | Renamed modwalker.h to modtools.h | Clifford Wolf | 2014-07-31 |
* | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 |
* | Added "trace" command | Clifford Wolf | 2014-07-31 |
* | Added RTLIL::Monitor | Clifford Wolf | 2014-07-31 |
* | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 |
* | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 |
* | Added "yosys -A" | Clifford Wolf | 2014-07-31 |
* | Added "yosys -Q" | Clifford Wolf | 2014-07-31 |
* | Added techmap CONSTMAP feature | Clifford Wolf | 2014-07-30 |
* | Added write_file command | Clifford Wolf | 2014-07-30 |
* | Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models | Clifford Wolf | 2014-07-30 |