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*
Added ID() macro for static IdStrings
Clifford Wolf
2014-08-03
*
Fixed a va_list corruption in logv_error()
Clifford Wolf
2014-08-02
*
Bugfix in "techmap -extern"
Clifford Wolf
2014-08-02
*
Removed at() method from RTLIL::IdString
Clifford Wolf
2014-08-02
*
No implicit conversion from IdString to anything else
Clifford Wolf
2014-08-02
*
More bugfixes related to new RTLIL::IdString
Clifford Wolf
2014-08-02
*
Limit size of log_signal buffer to 100 elements
Clifford Wolf
2014-08-02
*
Improvements in new RTLIL::IdString implementation
Clifford Wolf
2014-08-02
*
Implemented new reference counting RTLIL::IdString
Clifford Wolf
2014-08-02
*
Fixed memory corruption related to id2cstr()
Clifford Wolf
2014-08-02
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
*
Preparations for RTLIL::IdString redesign: cleanup of existing code
Clifford Wolf
2014-08-02
*
Added logfile hash to statistics footer
Clifford Wolf
2014-08-01
*
Added per-pass cpu usage statistics
Clifford Wolf
2014-08-01
*
Added ModIndex helper class, some changes to RTLIL::Monitor
Clifford Wolf
2014-08-01
*
Packed SigBit::data and SigBit::offset in a union
Clifford Wolf
2014-08-01
*
Renamed modwalker.h to modtools.h
Clifford Wolf
2014-07-31
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Added "trace" command
Clifford Wolf
2014-07-31
*
Added RTLIL::Monitor
Clifford Wolf
2014-07-31
*
Added module->design and cell->module, wire->module pointers
Clifford Wolf
2014-07-31
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
*
Added "yosys -A"
Clifford Wolf
2014-07-31
*
Added "yosys -Q"
Clifford Wolf
2014-07-31
*
Added techmap CONSTMAP feature
Clifford Wolf
2014-07-30
*
Added write_file command
Clifford Wolf
2014-07-30
*
Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models
Clifford Wolf
2014-07-30
*
Added "log_dump_val_worker(char *v)"
Clifford Wolf
2014-07-30
*
Added "kernel/yosys.h" and "kernel/yosys.cc"
Clifford Wolf
2014-07-30
*
Added "test_cell" command
Clifford Wolf
2014-07-29
*
Renamed "write_autotest" to "test_autotb" and moved to passes/tests/
Clifford Wolf
2014-07-29
*
Added "techmap -map %{design-name}"
Clifford Wolf
2014-07-29
*
Added $shift and $shiftx cell types (needed for correct part select behavior)
Clifford Wolf
2014-07-29
*
Added wire->upto flag for signals such as "wire [0:7] x;"
Clifford Wolf
2014-07-28
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
*
Added std::initializer_list<> constructor to SigSpec
Clifford Wolf
2014-07-28
*
Added cover() to all SigSpec constructors
Clifford Wolf
2014-07-28
*
Added proper Design->addModule interface
Clifford Wolf
2014-07-27
*
Added topological sorting to techmap
Clifford Wolf
2014-07-27
*
Added SigPool::check(bit)
Clifford Wolf
2014-07-27
*
Small improvements in PerformanceTimer API
Clifford Wolf
2014-07-27
*
Improved performance of opt_const on large modules
Clifford Wolf
2014-07-27
*
Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs
Clifford Wolf
2014-07-27
*
Added RTLIL::SigSpecConstIterator
Clifford Wolf
2014-07-27
*
Added log_cmd_error_expection
Clifford Wolf
2014-07-27
*
Added RTLIL::Module::wire(id) and cell(id) lookup functions
Clifford Wolf
2014-07-27
*
Added RTLIL::Design::modules()
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Added conversion from ObjRange to std::vector and std::set
Clifford Wolf
2014-07-27
*
Added RTLIL::ObjIterator and RTLIL::ObjRange
Clifford Wolf
2014-07-27
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