yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>	Clifford Wolf	2014-07-18
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*	Added function-like cell creation helpers	Clifford Wolf	2014-07-18
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*	Added log_id() helper function	Clifford Wolf	2014-07-18
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*	Fixed RTLIL::SigSpec::append_bit() for appending constants	Clifford Wolf	2014-07-17
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*	Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal	Clifford Wolf	2014-07-16
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*	Use "verilog -sv" to parse .sv files	Clifford Wolf	2014-07-11
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*	Add support for cell arrays	Clifford Wolf	2014-06-07
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*	Improved error message for options after front-end filename arguments	Clifford Wolf	2014-06-04
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*	workaround for OpenBSD 'stdout' implementation	Clifford Wolf	2014-05-03
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*	workaround for OpenBSD 'stdin' implementation	Clifford Wolf	2014-05-02
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*	Added support for dlatchsr cells	Clifford Wolf	2014-03-31
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*	Fixed typo in RTLIL::Module::addAdff()	Clifford Wolf	2014-03-17
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*	Fixed typo in RTLIL::Module::{addSshl,addSshr}	Clifford Wolf	2014-03-15
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*	Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API	Clifford Wolf	2014-03-15
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*	Added log_dump() support for generic pointers	Clifford Wolf	2014-03-14
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*	Progress in Verific bindings	Clifford Wolf	2014-03-14
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*	Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API	Clifford Wolf	2014-03-14
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*	Hotfix for kernel/compatibility.h	Clifford Wolf	2014-03-13
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*	Merged OSX fixes from Siesh1oo with some modifications	Clifford Wolf	2014-03-13
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*	- kernel/register.h, kernel/driver.cc: refactor ↵	Siesh1oo	2014-03-12
\| \| \| \| \| \| \|	rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems. - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
*	Added libs/minisat (copy of minisat git master)	Clifford Wolf	2014-03-12
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*	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11
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*	Fixed a typo in RTLIL::Module::addReduce...	Clifford Wolf	2014-03-10
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*	Added RTLIL::Module::add... helper methods	Clifford Wolf	2014-03-10
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*	Fixed use of frozen literals in SatGen	Clifford Wolf	2014-03-06
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*	Strictly zero-extend unsigned A-inputs of shift operations	Clifford Wolf	2014-03-06
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*	Fixed const folding of $bu0 cells	Clifford Wolf	2014-02-27
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*	Added support for $bu0 to SatGen	Clifford Wolf	2014-02-26
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*	Added support for Minisat::SimpSolver + ezSAT frezze() API	Clifford Wolf	2014-02-23
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*	Fixed small memory leak in Pass::call()	Clifford Wolf	2014-02-23
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*	Added "design -push" and "design -pop"	Clifford Wolf	2014-02-20
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*	Improved checking of internal cell conventions	Clifford Wolf	2014-02-08
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*	Added $slice and $concat to CellTypes list	Clifford Wolf	2014-02-07
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*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07
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*	Stronger checking of internal cells	Clifford Wolf	2014-02-07
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*	Added echo command	Clifford Wolf	2014-02-07
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*	Added generic RTLIL::SigSpec::parse_sel() with support for selection variables	Clifford Wolf	2014-02-06
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*	Added support for #-comments in same line as command	Clifford Wolf	2014-02-06
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*	Added support for backslash continuation in script files	Clifford Wolf	2014-02-06
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*	Fixed bug in sequential sat proofs and improved handling of asserts	Clifford Wolf	2014-02-04
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*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
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*	Added RTLIL::SigSpec::to_single_sigbit()	Clifford Wolf	2014-02-02
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*	Added yosys -H for command list	Clifford Wolf	2014-01-30
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*	Added -h command line option	Clifford Wolf	2014-01-29
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*	Added $assert support to satgen	Clifford Wolf	2014-01-19
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*	Added $assert cell	Clifford Wolf	2014-01-19
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*	Some improvements in log_dump_val_worker() templates	Clifford Wolf	2014-01-17
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*	Added select -assert-none and -assert-any	Clifford Wolf	2014-01-17
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*	Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux	Clifford Wolf	2014-01-03
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*	Added RTLIL::SigSpec::optimized() API	Clifford Wolf	2014-01-03
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