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path:
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passes
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abc
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abc.cc
Commit message (
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Author
Age
*
Added "abc -lut w1:w2"
Clifford Wolf
2015-01-15
*
Fixed typo in ABC command
Clifford Wolf
2014-12-30
*
Less verbose ABC output
Clifford Wolf
2014-12-29
*
Improved ABC clock domain partitioning
Clifford Wolf
2014-12-23
*
Added "abc -markgroups"
Clifford Wolf
2014-12-23
*
Added support for multiple clock domains to "abc" pass
Clifford Wolf
2014-12-21
*
Fixed "abc" pass for clk and enable signals driven by logic
Clifford Wolf
2014-12-21
*
Added DFFE support to "abc" pass
Clifford Wolf
2014-12-20
*
Also look for yosys-abc in parent dir on win32
Clifford Wolf
2014-10-18
*
Header changes so it will compile on VS
William Speirs
2014-10-17
*
More win32/abc fixes
Clifford Wolf
2014-10-12
*
Added make_temp_{file,dir}() and remove_directory() APIs
Clifford Wolf
2014-10-12
*
Using stringf() instead of asprintf() in "abc" pass
Clifford Wolf
2014-10-12
*
Added run_command() api to replace system() and popen()
Clifford Wolf
2014-10-12
*
Added API for generic cell cost calculations
Clifford Wolf
2014-10-09
*
Added $_BUF_ cell type
Clifford Wolf
2014-10-03
*
namespace Yosys
Clifford Wolf
2014-09-27
*
Small improvements in "abc" command handle_loops() function
Clifford Wolf
2014-09-19
*
Using "NOT" instead of "INV" as cell name in default abc genlib file
Clifford Wolf
2014-09-19
*
Do not run "scorr" in "abc -fast"
Clifford Wolf
2014-09-18
*
Added "abc -fast"
Clifford Wolf
2014-09-18
*
Fixed $_NOR vs. $_NOR_ typo in abc.cc
Clifford Wolf
2014-09-16
*
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...
Clifford Wolf
2014-08-16
*
Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
*
Added "abc -D" for setting delay target
Clifford Wolf
2014-08-14
*
Filter ANSI escape sequences from ABC output
Clifford Wolf
2014-08-13
*
No implicit conversion from IdString to anything else
Clifford Wolf
2014-08-02
*
Preparations for RTLIL::IdString redesign: cleanup of existing code
Clifford Wolf
2014-08-02
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
*
Replaced more old SigChunk programming patterns
Clifford Wolf
2014-07-24
*
Removed RTLIL::SigSpec::expand() method
Clifford Wolf
2014-07-23
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
Clifford Wolf
2014-07-23
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Clifford Wolf
2014-07-23
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
Clifford Wolf
2014-07-23
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
*
- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar...
Siesh1oo
2014-03-12
*
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
Clifford Wolf
2014-03-11
*
Verbose reading of liberty and constr files in ABC pass
Clifford Wolf
2014-03-09
*
Added abc -keepff option
Clifford Wolf
2014-02-14
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