Commit message (Expand) | Author | Age | |
---|---|---|---|
* | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 |
* | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 |
* | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 |
* | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 |
* | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 |
* | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 |
* | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 |
* | Removed deprecated module->new_wire() | Clifford Wolf | 2014-07-21 |
* | Added generic RTLIL::SigSpec::parse_sel() with support for selection variables | Clifford Wolf | 2014-02-06 |
* | Added "connect" command | Clifford Wolf | 2014-01-03 |