Commit message (Expand) | Author | Age | |
---|---|---|---|
* | New upstream version 0.7+20180830git0b7a184 | Ruben Undheim | 2018-08-30 |
* | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 |
* | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 |
* | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 |
* | Preparations for RTLIL::IdString redesign: cleanup of existing code | Clifford Wolf | 2014-08-02 |
* | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 |
* | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 |
* | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 |
* | Added "design -push" and "design -pop" | Clifford Wolf | 2014-02-20 |
* | Fixed use of "cmd_error" in passes/cmds/design.cc | Clifford Wolf | 2014-02-07 |
* | Added design -stash/-copy-from/-copy-to | Clifford Wolf | 2014-02-06 |
* | Added "design" command (-reset, -save, -load) | Clifford Wolf | 2013-07-27 |