Commit message (Expand) | Author | Age | |
---|---|---|---|
* | Import more std:: stuff into Yosys namespace | Clifford Wolf | 2015-10-25 |
* | improvement in "stat" | Clifford Wolf | 2015-10-24 |
* | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 |
* | Fixed "stat" handling of blackbox modules | Clifford Wolf | 2015-02-14 |
* | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 |
* | sort cell types in "stat" output by name | Clifford Wolf | 2014-10-03 |
* | namespace Yosys | Clifford Wolf | 2014-09-27 |
* | Removed $bu0 cell type | Clifford Wolf | 2014-09-04 |
* | Added "stat -width" | Clifford Wolf | 2014-08-22 |
* | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 |
* | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 |
* | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 |
* | Bugfixes in new "stat" command | Clifford Wolf | 2013-11-25 |
* | Added "stat" command | Clifford Wolf | 2013-11-25 |