yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
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*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
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*	Removed references to yosys-svgviewer from docs	Clifford Wolf	2014-09-02
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*	Using "xdot" instead of "yosys-svgviewer" in show command	Clifford Wolf	2014-09-02
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*	Moved "share" and "wreduce" to passes/opt/	Clifford Wolf	2014-09-01
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*	Implemented "rename -enumerate -pattern"	Clifford Wolf	2014-08-26
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*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23
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*	Added "stat -width"	Clifford Wolf	2014-08-22
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*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22
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*	Added "plugin" command	Clifford Wolf	2014-08-22
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*	Added module->uniquify()	Clifford Wolf	2014-08-16
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*	RIP $safe_pmux	Clifford Wolf	2014-08-14
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*	Fixed build with gcc-4.6	Clifford Wolf	2014-08-07
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*	Various fixes and improvements in wreduce pass	Clifford Wolf	2014-08-05
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*	Removed old "constmap" from wreduce code	Clifford Wolf	2014-08-05
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*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05
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*	Cleanups and improvements in wreduce pass	Clifford Wolf	2014-08-05
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*	Added mux support to wreduce command	Clifford Wolf	2014-08-05
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*	Added "show -signed"	Clifford Wolf	2014-08-04
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*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04
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*	Progress in "wreduce" pass	Clifford Wolf	2014-08-03
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*	Added "wreduce" command (work in progress)	Clifford Wolf	2014-08-03
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*	Fixes in show command (related to new IdString)	Clifford Wolf	2014-08-03
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*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02
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*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
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*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02
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*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
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*	Added "trace" command	Clifford Wolf	2014-07-31
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
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*	Added write_file command	Clifford Wolf	2014-07-30
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
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*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
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*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
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*	Various RTLIL::SigSpec related code cleanups	Clifford Wolf	2014-07-25
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*	Disabled cover() for non-linux builds	Clifford Wolf	2014-07-25
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*	Improvements in "cover" command	Clifford Wolf	2014-07-25
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*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
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*	Added "cover" command	Clifford Wolf	2014-07-24
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*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
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