Commit message (Expand) | Author | Age | |
---|---|---|---|
* | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 |
* | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 |
* | Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys | Clifford Wolf | 2014-03-11 |
* | Replaced RTLIL::Const::str with generic decoder method | Clifford Wolf | 2013-12-04 |
* | Improved FSM one-hot encoding, added binary encoding | Clifford Wolf | 2013-05-24 |
* | Added help messages for fsm_* passes | Clifford Wolf | 2013-03-01 |
* | initial import | Clifford Wolf | 2013-01-05 |