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* New upstream version 0.9Ruben Undheim2019-10-18
* Imported GIT HEAD: 0.8+20190328git32bd0f2Ruben Undheim2019-03-28
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Squashed commit of the following:Ruben Undheim2016-09-23
* Fixed some visual studio warningsClifford Wolf2016-02-13
* Bugfix in memory_dffClifford Wolf2015-10-31
* Added read-enable to memory modelClifford Wolf2015-09-25
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Modernized memory_dff (and fixed a bug)Clifford Wolf2015-06-14
* Merge clock inverters in memory_dffClifford Wolf2015-06-09
* namespace YosysClifford Wolf2014-09-27
* Fixed $memwr/$memrd order in memory_dffClifford Wolf2014-09-16
* Various improvements in memory_dff passClifford Wolf2014-08-06
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Using new obj iterator API in a few placesClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Fixed log messages in memory_dffClifford Wolf2014-06-01
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* A fix in memory_dff for write ports with static addressesClifford Wolf2013-12-01
* Added help messages to memory_* passesClifford Wolf2013-03-01
* initial importClifford Wolf2013-01-05