yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25
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*	renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()	Clifford Wolf	2015-10-24
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*	Added sat -show-regs, -show-public, -show-all	Clifford Wolf	2015-08-18
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*	Re-created command-reference-manual.tex, copied some doc fixes to online help	Clifford Wolf	2015-08-14
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*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14
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*	Added "miter -assert"	Clifford Wolf	2015-07-25
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
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*	Added logic-loop error handling to freduce	Clifford Wolf	2015-06-30
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*	don't consider blackbox modules in "sat" command	Clifford Wolf	2015-04-18
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*	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26
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*	Fixed "sat -initsteps" off-by-one bug	Clifford Wolf	2015-02-22
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*	Added "sat -stepsize" and "sat -tempinduct-step"	Clifford Wolf	2015-02-21
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*	sat docu change	Clifford Wolf	2015-02-21
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*	When "sat -tempinduct-baseonly -maxsteps N" reaches maxsteps it is a good thing.	Clifford Wolf	2015-02-21
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*	Added "sat -tempinduct-baseonly -tempinduct-inductonly"	Clifford Wolf	2015-02-21
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*	Fixed basecase init for "sat -tempinduct"	Clifford Wolf	2015-02-21
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*	Replaced ezDefaultSAT with ezSatPtr	Clifford Wolf	2015-02-21
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*	format fixes in "sat -dump_json"	Clifford Wolf	2015-02-19
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*	Added "sat -dump_json" (WaveJSON format)	Clifford Wolf	2015-02-19
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*	Improved an error message	Clifford Wolf	2015-01-28
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*	Added "sat -show-ports"	Clifford Wolf	2015-01-27
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*	Moved equiv stuff to passes/equiv/	Clifford Wolf	2015-01-22
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*	Progress in equiv_simple	Clifford Wolf	2015-01-21
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*	Added equiv_simple	Clifford Wolf	2015-01-19
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*	Added equiv_status	Clifford Wolf	2015-01-19
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*	Added equiv_make command	Clifford Wolf	2015-01-19
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*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24
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*	Added log_warning() API	Clifford Wolf	2014-11-09
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*	Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32	Clifford Wolf	2014-10-10
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*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
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*	namespace Yosys	Clifford Wolf	2014-09-27
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*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
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*	Fixes in old SAT example.ys	Clifford Wolf	2014-09-01
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*	Moved "share" and "wreduce" to passes/opt/	Clifford Wolf	2014-09-01
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*	azonenberg: Make dump_vcd save model when temporal induction fails due to ↵	Clifford Wolf	2014-08-24
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*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
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*	Fixed "share" for complex scenarios with never-active cells	Clifford Wolf	2014-08-09
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*	Do not share any $reduce_* cells (its complicated and not worth it anyways)	Clifford Wolf	2014-08-09
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*	Fixed sharing of reduce operator	Clifford Wolf	2014-08-08
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*	Added "sat -prove-skip"	Clifford Wolf	2014-08-08
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*	Use "-keepdc" in "miter -equiv -flatten"	Clifford Wolf	2014-08-07
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*	Fixed "share" for memory read ports	Clifford Wolf	2014-08-03
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*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02
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*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
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*	Renamed modwalker.h to modtools.h	Clifford Wolf	2014-07-31
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
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