Commit message (Collapse) | Author | Age | |
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* | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 |
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* | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 |
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* | Changed more code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 |
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* | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 |
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* | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 |
| | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | ||
* | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 |
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* | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 |
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* | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 |
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* | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 |
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* | Added support for "blackbox" attribute to iopadmap | Clifford Wolf | 2014-07-17 |
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* | Added iopadmap -bits | Clifford Wolf | 2014-02-15 |
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* | Added support for i/o buffers to iopadmap | Clifford Wolf | 2013-10-26 |
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* | Fixed handling of boolean attributes (passes) | Clifford Wolf | 2013-10-24 |
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* | Added iopadmap pass | Clifford Wolf | 2013-10-16 |