yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added "test_autotb -n <num_iter>" option	Clifford Wolf	2014-08-01
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*	Renamed modwalker.h to modtools.h	Clifford Wolf	2014-07-31
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
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*	Added "trace" command	Clifford Wolf	2014-07-31
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
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*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31
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*	Added "techmap -assert"	Clifford Wolf	2014-07-31
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*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30
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*	Added write_file command	Clifford Wolf	2014-07-30
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*	Improvements in test_cell	Clifford Wolf	2014-07-30
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*	Added "test_cell" command	Clifford Wolf	2014-07-29
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*	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29
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*	Allow "hierarchy -generate" for $__ cells	Clifford Wolf	2014-07-29
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*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
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*	Added techmap -extern	Clifford Wolf	2014-07-27
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*	Added topological sorting to techmap	Clifford Wolf	2014-07-27
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*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27
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*	Fixed bug in opt_clean	Clifford Wolf	2014-07-27
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*	Improved performance of opt_const on large modules	Clifford Wolf	2014-07-27
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*	Fixed a bug in opt_clean and some RTLIL API usage cleanups	Clifford Wolf	2014-07-27
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*	Added log_cmd_error_expection	Clifford Wolf	2014-07-27
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*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
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*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
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*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26
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*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
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*	Added copy-constructor-like module->addCell(name, other) method	Clifford Wolf	2014-07-26
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
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*	Various RTLIL::SigSpec related code cleanups	Clifford Wolf	2014-07-25
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*	Fixed memory corruption in "opt_reduce" pass	Clifford Wolf	2014-07-25
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*	Disabled cover() for non-linux builds	Clifford Wolf	2014-07-25
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*	Improvements in "cover" command	Clifford Wolf	2014-07-25
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*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
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*	Added cover() calls to opt_const	Clifford Wolf	2014-07-24
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*	Added "make SMALL=1"	Clifford Wolf	2014-07-24
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*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24
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*	Added "cover" command	Clifford Wolf	2014-07-24
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*	Various small fixes (from gcc compiler warnings)	Clifford Wolf	2014-07-23
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*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
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*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23
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*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23
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