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path: root/techlibs/ice40/cells_sim.v
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* Fixed trailing whitespacesClifford Wolf2015-07-02
* Added iCE40 PLL cellsClifford Wolf2015-05-31
* improved ice40 SB_IO sim modelClifford Wolf2015-05-23
* Added ice40 SB_IO sim modelClifford Wolf2015-05-23
* improved iCE40 SB_RAM40_4K simulation modelClifford Wolf2015-04-25
* More iCE40 bram improvementsClifford Wolf2015-04-25
* iCE40 bram tests and fixesClifford Wolf2015-04-24
* iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* modelsClifford Wolf2015-04-19
* Changed ice40 ICESTORM_CARRYCONST port nameClifford Wolf2015-04-16
* improved ice40 dff cell mappingClifford Wolf2015-04-16
* more cells in ice40 cell libraryClifford Wolf2015-04-14
* Added very first version of "synth_ice40"Clifford Wolf2015-03-05