index
:
yosys
master
Debian dgit repo for package yosys
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
techlibs
Commit message (
Expand
)
Author
Age
*
Added $meminit support to "memory" command
Clifford Wolf
2015-02-14
*
Added $meminit cell type
Clifford Wolf
2015-02-14
*
Added "check" command
Clifford Wolf
2015-02-13
*
Some test related fixes
Clifford Wolf
2015-02-12
*
Disabled (unused) Xilinx tristate buffers
Clifford Wolf
2015-02-04
*
no support for 6-series xilinx devices
Clifford Wolf
2015-02-01
*
Removed old XST-based xilinx examples
Clifford Wolf
2015-02-01
*
Added Xilinx example for Basys3 board
Clifford Wolf
2015-02-01
*
Added missing ports and parameters to xilinx brams
Clifford Wolf
2015-02-01
*
Added "make mklibyosys", some minor API changes
Clifford Wolf
2015-02-01
*
Added "fsm -encfile"
Clifford Wolf
2015-01-30
*
Fixed xilinx FDSE sim model
Clifford Wolf
2015-01-24
*
Added $equiv cell type
Clifford Wolf
2015-01-19
*
Various cleanups in xilinx techlib
Clifford Wolf
2015-01-18
*
Refactoring of memory_bram and xilinx brams
Clifford Wolf
2015-01-18
*
Added synth_xilinx -retime -flatten
Clifford Wolf
2015-01-17
*
Added MUXCY and XORCY support to synth_xilinx
Clifford Wolf
2015-01-17
*
Added cells.lib
Clifford Wolf
2015-01-16
*
Added dff2dffe to synth_xilinx
Clifford Wolf
2015-01-16
*
Added more FF types to xilinx/cells.v
Clifford Wolf
2015-01-16
*
Fixed xilinx bram clock inverted config
Clifford Wolf
2015-01-16
*
Added FF cells to xilinx/cells_sim.v
Clifford Wolf
2015-01-16
*
Added Xilinx MUXF7 and MUXF8 support
Clifford Wolf
2015-01-15
*
Various cleanups in synth_xilinx command
Clifford Wolf
2015-01-13
*
Added add_share_file Makefile macro
Clifford Wolf
2015-01-08
*
added minimalistic xilinx sim models
Clifford Wolf
2015-01-08
*
More Xilinx bram cleanups
Clifford Wolf
2015-01-07
*
Cleanups in xilinx bram descriptions
Clifford Wolf
2015-01-07
*
Xilinx RAMB36/RAMB18 memory_bram support complete
Clifford Wolf
2015-01-06
*
Towards Xilinx bram support
Clifford Wolf
2015-01-06
*
small fix in xilinx/brams.v
Clifford Wolf
2015-01-06
*
Towards Xilinx bram support
Clifford Wolf
2015-01-06
*
Various small improvements to synth_xilinx
Clifford Wolf
2015-01-06
*
Towards Xilinx bram support
Clifford Wolf
2015-01-06
*
Towards Xilinx bram support
Clifford Wolf
2015-01-06
*
Towards Xilinx bram support
Clifford Wolf
2015-01-05
*
Towards Xilinx bram support
Clifford Wolf
2015-01-04
*
Progress in memory_bram
Clifford Wolf
2015-01-03
*
Added proper clkpol support to memory_bram
Clifford Wolf
2015-01-02
*
New $mem simlib model
Clifford Wolf
2015-01-02
*
Progress in memory_bram
Clifford Wolf
2014-12-31
*
Added memory_bram (not functional yet)
Clifford Wolf
2014-12-31
*
Fixed simlib entries for $memrd and $memwr
Clifford Wolf
2014-12-30
*
Fixed build with SMALL=1
Clifford Wolf
2014-12-30
*
Improvements in simplemap api, added $ne $nex $eq $eqx support
Clifford Wolf
2014-12-24
*
Removed UTF-8 chars from techmap.v
Clifford Wolf
2014-12-12
*
Added $dffe cell type
Clifford Wolf
2014-12-08
*
Added $_DFFE_??_ cell types
Clifford Wolf
2014-12-08
*
Added "abc" label in synth script
Clifford Wolf
2014-10-31
*
Added "opt -full" alias for all more aggressive optimizations
Clifford Wolf
2014-10-31
[next]