| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | Fixed a bug in AST frontend for cases with non-blocking assigned variables ↵ | Clifford Wolf | 2013-04-13 |
| | | | | | as case values | ||
| * | Added test cases from 2012 paper on comparison of foss verilog synthesis tools | Clifford Wolf | 2013-03-31 |
| | | |||
| * | Renamed hansimem.v test case to mem_arst.v | Clifford Wolf | 2013-03-24 |
| | | |||
| * | Added hansimem testcase (memory with async reset) | Clifford Wolf | 2013-03-24 |
| | | |||
| * | added ckeck for Icarus Verilog, otherwise the tests are silently stopped | Johann Glaser | 2013-03-17 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||
| * | added more .gitignore files (make test) | Clifford Wolf | 2013-01-05 |
| | | |||
| * | initial import | Clifford Wolf | 2013-01-05 |
 |
index : yosys | |
| Debian dgit repo for package yosys |
| summaryrefslogtreecommitdiff |