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Age
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Various ast changes for early expression width detection (prep for constfold ...
Clifford Wolf
2013-11-02
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Added support for complex set-reset flip-flops in proc_dff
Clifford Wolf
2013-10-24
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Improved handling of dff with async resets
Clifford Wolf
2013-10-21
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Moved common techlib files to techlibs/common
Clifford Wolf
2013-09-15
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Added support for "2**n" shifter encoding
Clifford Wolf
2013-08-12
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Added $div and $mod technology mapping
Clifford Wolf
2013-08-09
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More fixes in ternary op sign handling
Clifford Wolf
2013-07-12
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Fixed sign handling in ternary operator
Clifford Wolf
2013-07-12
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Another vloghammer related bugfix
Clifford Wolf
2013-07-11
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More fixes in ast expression sign/width handling
Clifford Wolf
2013-07-09
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Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2013-07-09
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Major redesign of expr width/sign detecion (verilog/ast frontend)
Clifford Wolf
2013-07-09
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Fixed shift ops with large right hand side
Clifford Wolf
2013-07-09
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Fixed another bug found using vloghammer
Clifford Wolf
2013-07-07
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Removed tests/xsthammer
Clifford Wolf
2013-07-07
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Fixed vivado related xsthammer bugs
Clifford Wolf
2013-07-05
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Various improvements in xsthammer report generator
Clifford Wolf
2013-07-05
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Added work-around to isim bug in xsthammer report script
Clifford Wolf
2013-07-05
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Added CARRY4 Xilinx cell to xsthammer cell lib
Clifford Wolf
2013-07-05
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Added xsthammer report generator
Clifford Wolf
2013-07-05
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Improved xsthammer quartus support
Clifford Wolf
2013-07-04
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Added Altera Cyclon III cell library to xsthammer
Clifford Wolf
2013-07-04
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Added defparam support to Verilog/AST frontend
Clifford Wolf
2013-07-04
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Added Altera Quartus support to xsthammer
Clifford Wolf
2013-07-03
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Progress in xsthammer
Clifford Wolf
2013-07-03
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Added vivado support to xsthammer
Clifford Wolf
2013-06-26
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Added timout functionality to SAT solver
Clifford Wolf
2013-06-20
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Added "eval" pass
Clifford Wolf
2013-06-19
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Added more stuff to xsthammer, found first xst bug
Clifford Wolf
2013-06-17
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Added ternary op and concat op to xsthammer
Clifford Wolf
2013-06-15
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Added consteval testing to xsthammer and fixed bugs
Clifford Wolf
2013-06-13
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More xsthammer improvements (using xst 14.5 now)
Clifford Wolf
2013-06-13
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Another fix for a bug found using xsthammer
Clifford Wolf
2013-06-12
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Further improved and extended xsthammer
Clifford Wolf
2013-06-11
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More xsthammer improvements
Clifford Wolf
2013-06-10
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Progress xsthammer scripts
Clifford Wolf
2013-06-10
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Progress in xsthammer: working proof for cell models
Clifford Wolf
2013-06-10
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Progress on xsthammer
Clifford Wolf
2013-06-10
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Added first xsthammer scripts
Clifford Wolf
2013-06-10
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Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
Clifford Wolf
2013-05-24
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Removed test cases that have been moved to yosys-test.
Clifford Wolf
2013-05-17
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Improved vcdcd.pl (added -d option)
Clifford Wolf
2013-05-14
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Some improvements in vcdcd.pl
Clifford Wolf
2013-05-14
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Fixed a bug in AST frontend for cases with non-blocking assigned variables as...
Clifford Wolf
2013-04-13
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Now only use value from "initial" when no matching "always" block is found
Clifford Wolf
2013-03-31
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
Clifford Wolf
2013-03-31
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Added k68 (m68k compatible cpu) test case from verilator
Clifford Wolf
2013-03-31
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Renamed hansimem.v test case to mem_arst.v
Clifford Wolf
2013-03-24
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Added hansimem testcase (memory with async reset)
Clifford Wolf
2013-03-24
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Set execute bit on tests/openmsp430/run-synth.sh for real
Clifford Wolf
2013-03-17
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