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Source: yosys
Section: universe/electronics
Priority: extra
Maintainer: Ruben Undheim <ruben.undheim@gmail.com>
Build-Depends: debhelper (>= 9), tcl8.5-dev, libqt4-dev, libqt4-opengl-dev, libqtwebkit-dev, libreadline-dev, git, zlib1g-dev, bison, flex, mercurial, iverilog, minisat
Standards-Version: 3.9.2
Homepage: http://www.clifford.at/yosys
#Vcs-Git: https://github.com/cliffordwolf/yosys.git
Package: yosys
Architecture: any
Depends: ${shlibs:Depends}, ${misc:Depends}, iverilog, graphviz
Description: Open source synthesis of digital circuits
yosys is a complete package for the synthesis from RTL to gate-level logic.
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