techlibs/xilinx/drams.txt


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

bram $__XILINX_RAM32X1D
  init 1
  abits 5
  dbits 1
  groups 2
  ports  1 1
  wrmode 0 1
  enable 0 1
  transp 0 0
  clocks 0 1
  clkpol 0 2
endbram

match $__XILINX_RAM32X1D
endmatch