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path:
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/
tests
/
errors
/
syntax_err07.v
blob: 62bcc6b3ed9ebb51f419c1cbaa088ecce85243fd (
plain
)
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module
a
;
wire
[
5
:
0
]
x
;
wire
[
3
:
0
]
y
;
assign
y
=
(
4
)
55
;
endmodule
