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path:
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/
tests
/
hana
/
test_simulation_seq_ff_1_test.v
blob: 5aac49c03e2bbcf224357ad3bda977080d00a736 (
plain
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module
test
(
input
in
,
input
clk
,
output
reg
out
);
always
@(
posedge
clk
)
out
<=
in
;
endmodule