blob: 8018de4ca9410ca890522ed1c8f6683b610e515e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
|
module top (input logic clk, input logic selA, selB, QA, QB, output logic Q);
always @(posedge clk) begin
if (selA) Q <= QA;
if (selB) Q <= QB;
end
check_selA: assert property ( @(posedge clk) selA |=> Q == $past(QA) );
check_selB: assert property ( @(posedge clk) selB |=> Q == $past(QB) );
`ifndef FAIL
assume_not_11: assume property ( @(posedge clk) !(selA & selB) );
`endif
endmodule
|
