| Commit message (Collapse) | Author | Age |
|---|
| |
|
|
|
|
| |
"yosys_debug" and the non-debug behavior is the default
(resulting in smaller layouts with fewer unconnected outputs
that are useful only for debugging).
|
| |
|
|
|
| |
process RTL in the verilog source, but only added it to the
preliminary yosys script, not to the final one.
|
| |
|
|
|
|
|
|
|
|
| |
the placement script, not the synthesis script. The change is
required due to the introduction of density planning, since the
density affects the generation of the .cel file passed to
graywolf for placement. If the .cel file is generated as part
of the synthesis script, then if the density is modified, the
flow has to be re-run from synthesis, not from placement. This
update corrects the issue.
|
| |
|
|
| |
synthesis flow scripts.
|
| |
|
|
|
| |
techlef, gds, spice, liberty) can be specified as absolute
paths and not have to be symbolic links from the tech directory.
|
| |
|
|
|
| |
failure to find a verilog source file. Helps to catch and
resolve gross errors faster.
|
| |
|
|
|
|
|
|
|
|
|
| |
to ABC that works much better than the default behavior, expanding
the range of cells used (e.g., will use AOI and OAI cells instead
of trying to shove everything into NAND/NOR logic). The practical
impact appears to be an increase in circuit speed as well as
routing efficiency. Added an additional hook from variable
"abc_script" in project_vars.sh for manual control over this
expression. 'set abc_script = ""' reverts to the original
behavior.
|
| |
|
|
|
|
|
|
|
| |
Corrected synthesis script to no longer require a "gate.cfg" file
to run blifFanout, since this has been deprecated (and is no longer
in the set of installed files). Modified blifFanout to use the
first buffer found in the liberty file, so details of the buffer
cell do not need to be provided in the tech shell script (although
they will be used, if passed to the program).
|
| |
|
|
|
|
|
| |
If set to 1, the yosys script uses "clean -purge" after the
standard cell mapping. This removes all the buffers that are
used to maintain internal signal names, resulting in a smaller
but less easily debugged layout.
|
| |
|
|
| |
"synth -top <rootname>" command, for yosys versions 0.5 and up.
|
| |
|
