diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-12-28 19:24:24 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-28 19:24:24 +0100 |
| commit | 137f35373f4ef0d1ddf212187e537e48d077b1f4 (patch) | |
| tree | a77df3913cb442b444f530648b71d4777e0921d2 /frontends/ast/ast.h | |
| parent | f3a97b75c78bd6f3670445129405213c0a015481 (diff) | |
Changed more code to dict<> and pool<>
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 27cf0ef3..1a7ac576 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -231,7 +231,7 @@ namespace AST // for expressions the resulting signal vector is returned // all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module RTLIL::SigSpec genRTLIL(int width_hint = -1, bool sign_hint = false); - RTLIL::SigSpec genWidthRTLIL(int width, const std::map<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL); + RTLIL::SigSpec genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL); // compare AST nodes bool operator==(const AstNode &other) const; @@ -293,7 +293,7 @@ namespace AST_INTERNAL extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; extern AST::AstNode *current_ast, *current_ast_mod; extern std::map<std::string, AST::AstNode*> current_scope; - extern const std::map<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr; + extern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr; extern RTLIL::SigSpec ignoreThisSignalsInInitial; extern AST::AstNode *current_top_block, *current_block, *current_block_child; extern AST::AstModule *current_module; |