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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-24 19:57:42 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-24 19:57:42 +0100 |
| commit | 7d9a90396d119375567b42eb0ff4bb120c355d9a (patch) | |
| tree | 288b3027be14d0e2d42d394a86a57aaa45d65b67 /frontends/ast/ast.h | |
| parent | 20175afd298be717aa91a96c9d8654859cf2dd2d (diff) | |
Added verilog frontend -ignore_redef option
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 34983225..fccabbe6 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -219,7 +219,7 @@ namespace AST }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code - void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false); + void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false, bool ignore_redef = false); // parametric modules are supported directly by the AST library // therfore we need our own derivate of RTLIL::Module with overloaded virtual functions |