Imported GIT HEAD: 0.8+20190328git32bd0f2

1 files changed, 17 insertions, 1 deletions

diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 7e97bdb3..ddd59d4b 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -142,6 +142,11 @@ namespace AST
 		AST_NEGEDGE,
 		AST_EDGE,
 
+		AST_INTERFACE,
+		AST_INTERFACEPORT,
+		AST_INTERFACEPORTTYPE,
+		AST_MODPORT,
+		AST_MODPORTMEMBER,
 		AST_PACKAGE
 	};
 
@@ -209,6 +214,8 @@ namespace AST
 			MEM2REG_FL_SET_ASYNC = 0x00000800,
 			MEM2REG_FL_EQ2       = 0x00001000,
 			MEM2REG_FL_CMPLX_LHS = 0x00002000,
+			MEM2REG_FL_CONST_LHS = 0x00004000,
+			MEM2REG_FL_VAR_LHS   = 0x00008000,
 
 			/* proc flags */
 			MEM2REG_FL_EQ1       = 0x01000000,
@@ -232,6 +239,7 @@ namespace AST
 		bool has_const_only_constructs(bool &recommend_const_eval);
 		void replace_variables(std::map<std::string, varinfo_t> &variables, AstNode *fcall);
 		AstNode *eval_const_function(AstNode *fcall);
+		bool is_simple_const_expr();
 
 		// create a human-readable text representation of the AST (for debugging)
 		void dumpAst(FILE *f, std::string indent) const;
@@ -274,7 +282,7 @@ namespace AST
 	};
 
 	// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
-	void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit,
+	void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit,
 			bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire);
 
 	// parametric modules are supported directly by the AST library
@@ -284,6 +292,9 @@ namespace AST
 		bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire;
 		~AstModule() YS_OVERRIDE;
 		RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail) YS_OVERRIDE;
+		RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail) YS_OVERRIDE;
+		std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool mayfail);
+		void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces) YS_OVERRIDE;
 		RTLIL::Module *clone() const YS_OVERRIDE;
 	};
 
@@ -300,6 +311,11 @@ namespace AST
 
 	// call a DPI function
 	AstNode *dpi_call(const std::string &rtype, const std::string &fname, const std::vector<std::string> &argtypes, const std::vector<AstNode*> &args);
+
+	// Helper functions related to handling SystemVerilog interfaces
+	std::pair<std::string,std::string> split_modport_from_type(std::string name_type);
+	AstNode * find_modport(AstNode *intf, std::string name);
+	void explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport);
 }
 
 namespace AST_INTERNAL