diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-02-17 14:28:52 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-17 14:28:52 +0100 |
| commit | 02e6f2c5be8c5514cc8cdb7b3344f6170fb87af9 (patch) | |
| tree | e5adb1a2baa9eba28f7c28bf755d00da266bfe52 /frontends/verilog/verilog_frontend.h | |
| parent | 0851c2b6ea7044d9bce2014a2be2365a2bf7e1b0 (diff) | |
Added Verilog support for "`default_nettype none"
Diffstat (limited to 'frontends/verilog/verilog_frontend.h')
| -rw-r--r-- | frontends/verilog/verilog_frontend.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h index 8b4fae6e..99b2164e 100644 --- a/frontends/verilog/verilog_frontend.h +++ b/frontends/verilog/verilog_frontend.h @@ -42,6 +42,9 @@ namespace VERILOG_FRONTEND // this function converts a Verilog constant to an AST_CONSTANT node AST::AstNode *const2ast(std::string code, char case_type = 0); + + // state of `default_nettype + extern bool default_nettype_wire; } // the pre-processor |