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authorClifford Wolf <clifford@clifford.at>2014-12-29 14:30:33 +0100
committerClifford Wolf <clifford@clifford.at>2014-12-29 14:30:33 +0100
commit0bb6b24c117fa685dce34abf82cb0f9ef73a7661 (patch)
treeeac781200c0eb5e4ff52debcac488cb6d621027e /kernel/yosys.cc
parentecd64182c5a3689ef293bccf032e1d7eecada91a (diff)
Added global yosys_celltypes
Diffstat (limited to 'kernel/yosys.cc')
-rw-r--r--kernel/yosys.cc9
1 files changed, 9 insertions, 0 deletions
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 6bc8dd0b..444bdb1d 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -18,6 +18,7 @@
*/
#include "kernel/yosys.h"
+#include "kernel/celltypes.h"
#ifdef YOSYS_ENABLE_READLINE
# include <readline/readline.h>
@@ -51,6 +52,7 @@ YOSYS_NAMESPACE_BEGIN
int autoidx = 1;
int yosys_xtrace = 0;
RTLIL::Design *yosys_design = NULL;
+CellTypes yosys_celltypes;
#ifdef YOSYS_ENABLE_TCL
Tcl_Interp *yosys_tcl_interp = NULL;
@@ -378,8 +380,14 @@ int GetSize(RTLIL::Wire *wire)
void yosys_setup()
{
+ // if there are already IdString objects then we have a global initialization order bug
+ IdString empty_id;
+ log_assert(empty_id.index_ == 0);
+ IdString::get_reference(empty_id.index_);
+
Pass::init_register();
yosys_design = new RTLIL::Design;
+ yosys_celltypes.setup();
log_push();
}
@@ -397,6 +405,7 @@ void yosys_shutdown()
log_files.clear();
Pass::done_register();
+ yosys_celltypes.clear();
#ifdef YOSYS_ENABLE_TCL
if (yosys_tcl_interp != NULL) {