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authorClifford Wolf <clifford@clifford.at>2014-07-26 00:38:44 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 00:38:44 +0200
commit4755e14e7b9ba57ea21bec4c0d0b3ac6080307e4 (patch)
treee77060cca5dcdb2bff334096fe55981208a57ab2 /kernel
parent2bec47a4045d23d46e7d300cbf80b2dce1a549a9 (diff)
Added copy-constructor-like module->addCell(name, other) method
Diffstat (limited to 'kernel')
-rw-r--r--kernel/rtlil.cc19
-rw-r--r--kernel/rtlil.h1
2 files changed, 12 insertions, 8 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 17e4a273..1a6e386f 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -782,14 +782,8 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
for (auto &it : memories)
new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
- for (auto &it : cells) {
- new_mod->cells[it.first] = new RTLIL::Cell;
- new_mod->cells[it.first]->name = it.second->name;
- new_mod->cells[it.first]->type = it.second->type;
- new_mod->cells[it.first]->connections = it.second->connections;
- new_mod->cells[it.first]->parameters = it.second->parameters;
- new_mod->cells[it.first]->attributes = it.second->attributes;
- }
+ for (auto &it : cells)
+ new_mod->addCell(it.first, it.second);
for (auto &it : processes)
new_mod->processes[it.first] = it.second->clone();
@@ -912,6 +906,15 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
return cell;
}
+RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
+{
+ RTLIL::Cell *cell = addCell(name, other->type);
+ cell->connections = other->connections;
+ cell->parameters = other->parameters;
+ cell->attributes = other->attributes;
+ return cell;
+}
+
#define DEF_METHOD(_func, _y_size, _type) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
RTLIL::Cell *cell = new RTLIL::Cell; \
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index e1e4a54b..fbd6e719 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -302,6 +302,7 @@ struct RTLIL::Module
RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
+ RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
// The add* methods create a cell and return the created cell. All signals must exist in advance.