diff options
author | Clifford Wolf <clifford@clifford.at> | 2013-07-20 15:19:12 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-07-20 15:19:12 +0200 |
commit | 61ed6b32d1f5fbfda9c6effdaa678092f8156bfa (patch) | |
tree | 3a53692cbd93a09eabeb67eff5e9e4ace5cf1a3e /manual/FILES_Eval/openmsp430.prj | |
parent | 3650fd7fbe45a00792770d9ecb9397bc27ea0845 (diff) |
Added Yosys Manual
Diffstat (limited to 'manual/FILES_Eval/openmsp430.prj')
-rw-r--r-- | manual/FILES_Eval/openmsp430.prj | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/manual/FILES_Eval/openmsp430.prj b/manual/FILES_Eval/openmsp430.prj new file mode 100644 index 00000000..cb8cd271 --- /dev/null +++ b/manual/FILES_Eval/openmsp430.prj @@ -0,0 +1,14 @@ +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_cell.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_reset.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_register_file.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg_uart.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_alu.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_watchdog.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sfr.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_multiplier.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_mem_backbone.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_frontend.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_execution_unit.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_clock_module.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/openMSP430.v" |