diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-02-16 14:32:56 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-16 14:32:56 +0100 |
| commit | aeb36b0b8b499a5b758840998afe9f1b4d7fc166 (patch) | |
| tree | 79ad73d969f02df836461d23040659b596f8c1fb /manual/PRESENTATION_ExAdv | |
| parent | 9c29969bbc1b19f251011feaa791d242ac8e5e81 (diff) | |
Progress in presentation
Diffstat (limited to 'manual/PRESENTATION_ExAdv')
| -rw-r--r-- | manual/PRESENTATION_ExAdv/Makefile | 5 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExAdv/sym_mul_cells.v | 6 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExAdv/sym_mul_map.v | 15 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExAdv/sym_mul_test.v | 5 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExAdv/sym_mul_test.ys | 6 |
5 files changed, 36 insertions, 1 deletions
diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile index 673b3a21..4ee5886d 100644 --- a/manual/PRESENTATION_ExAdv/Makefile +++ b/manual/PRESENTATION_ExAdv/Makefile @@ -1,5 +1,5 @@ -all: select_01.pdf red_or3x1.pdf +all: select_01.pdf red_or3x1.pdf sym_mul.pdf select_01.pdf: select_01.v select_01.ys ../../yosys select_01.ys @@ -7,3 +7,6 @@ select_01.pdf: select_01.v select_01.ys red_or3x1.pdf: red_or3x1_* ../../yosys red_or3x1_test.ys +sym_mul.pdf: sym_mul_* + ../../yosys sym_mul_test.ys + diff --git a/manual/PRESENTATION_ExAdv/sym_mul_cells.v b/manual/PRESENTATION_ExAdv/sym_mul_cells.v new file mode 100644 index 00000000..ce177154 --- /dev/null +++ b/manual/PRESENTATION_ExAdv/sym_mul_cells.v @@ -0,0 +1,6 @@ +module MYMUL(A, B, Y); + parameter WIDTH = 1; + input [WIDTH-1:0] A, B; + output [WIDTH-1:0] Y; + assign Y = A * B; +endmodule diff --git a/manual/PRESENTATION_ExAdv/sym_mul_map.v b/manual/PRESENTATION_ExAdv/sym_mul_map.v new file mode 100644 index 00000000..293c5b84 --- /dev/null +++ b/manual/PRESENTATION_ExAdv/sym_mul_map.v @@ -0,0 +1,15 @@ +module \$mul (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH != Y_WIDTH; + + MYMUL #( .WIDTH(Y_WIDTH) ) g ( .A(A), .B(B), .Y(Y) ); +endmodule diff --git a/manual/PRESENTATION_ExAdv/sym_mul_test.v b/manual/PRESENTATION_ExAdv/sym_mul_test.v new file mode 100644 index 00000000..eb715f83 --- /dev/null +++ b/manual/PRESENTATION_ExAdv/sym_mul_test.v @@ -0,0 +1,5 @@ +module test(A, B, C, Y1, Y2); + input [7:0] A, B, C; + output [7:0] Y1 = A * B; + output [15:0] Y2 = A * C; +endmodule diff --git a/manual/PRESENTATION_ExAdv/sym_mul_test.ys b/manual/PRESENTATION_ExAdv/sym_mul_test.ys new file mode 100644 index 00000000..0c07e7e8 --- /dev/null +++ b/manual/PRESENTATION_ExAdv/sym_mul_test.ys @@ -0,0 +1,6 @@ +read_verilog sym_mul_test.v +hierarchy -check -top test + +techmap -map sym_mul_map.v;; + +show -prefix sym_mul -format pdf -notitle -lib sym_mul_cells.v |