diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 16:38:54 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 16:38:54 +0200 |
| commit | cdae8abe16847c533171fed111beea7b52202cce (patch) | |
| tree | bf8dddb4a4ca4d70c83603ef61b2d22cb95d153a /passes/hierarchy | |
| parent | b5a9e51b966abdfedc9309defa79b5141928e84a (diff) | |
Renamed port access function on RTLIL::Cell, added param access functions
Diffstat (limited to 'passes/hierarchy')
| -rw-r--r-- | passes/hierarchy/submod.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index d0c9f4b5..2a47002e 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -185,7 +185,7 @@ struct SubmodWorker RTLIL::Wire *old_wire = it.first; RTLIL::Wire *new_wire = it.second.new_wire; if (new_wire->port_id > 0) - new_cell->set(new_wire->name, RTLIL::SigSpec(old_wire)); + new_cell->setPort(new_wire->name, RTLIL::SigSpec(old_wire)); } } |