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authorClifford Wolf <clifford@clifford.at>2014-08-15 02:40:46 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-15 02:40:46 +0200
commitca8711644975c128d45fd8e9434439c1266c00ac (patch)
treed142e82fe2dbdebf77635a05862b383c81167e3b /passes/opt/opt_clean.cc
parent8ff71b5ae506306d7981eb118874cd4f407b2bf8 (diff)
More idstring sort_by_* helpers and fixed tpl ordering in techmap
Diffstat (limited to 'passes/opt/opt_clean.cc')
-rw-r--r--passes/opt/opt_clean.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index c620531e..d47e4513 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -34,7 +34,7 @@ static int count_rm_cells, count_rm_wires;
static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
{
SigMap assign_map(module);
- std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> queue, unused;
+ std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> queue, unused;
SigSet<RTLIL::Cell*> wire2driver;
for (auto &it : module->cells_) {
@@ -65,7 +65,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
while (queue.size() > 0)
{
- std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> new_queue;
+ std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> new_queue;
for (auto cell : queue)
unused.erase(cell);
for (auto cell : queue) {